GATE CSE 2010 | Question: 49

Question

A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ nanoseconds, $20$ nanoseconds and $200$ nanoseconds for $L1$ cache, $L2$ cache and the main memory unit respectively.

 

When there is a miss in both $L1$ cache and $L2$ cache, first a block is transferred from main memory to $L2$ cache, and then a block is transferred from $L2$ cache to $L1$ cache. What is the total time taken for these transfers?

• A. $222$ nanoseconds
• B. $888$ nanoseconds
• C. $902$ nanoseconds
• D. $968$ nanoseconds

Comments

During a transfer cycle, moving data from a source memory to a destination cache requires both reading from the source ($T_{\text{read}}$) and writing into the destination ($T_{\text{write}}$) for each bus cycle....

Main Memory ==>  L2: $4 \times (200\text{ ns read} + 20\text{ ns write}) = 880\text{ ns}$

L2 ==> L1: $1 \times (20\text{ ns read} + 2\text{ ns write}) = 22\text{ ns}$

Total Transfer Time: $880 + 22 = 902\text{ ns}$

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These questions should have been challanged back then...

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i not get why we not do like 880 + 88 since :

  main memory to l2 = 4 * ( l2 read + mm read )   = 880 ns

so  t2 to l1 = 4 * ( l1 read + l2 read )  = 88  ns

so option d  968 ns

why we not do like this

 

Answer 1

The transfer time should be $4*200 + 20 = 820$ ns. But this is not in option. So, I assume the following is what is meant by the question.

$L2$ block size being $16$ words and data width between memory and $L2$ being $4$ words, we require $4$ memory accesses(for read) and $4$ $L2$ accesses (for store). Now, we need to send the requested block to $L1$ which would require one more $L2$ access (for read) and one $L1$ access (for store). So, total time

$= 4 * (200 + 20) +  (20 + 2)$

$= 880 + 22$

$= 902 \ ns$

Correct Answer: $C$

Comments

Very poorly framed question it is, they should specify that we need to include the time store, Because many similar gate questions we assume only access time.

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In one memory access time we can access only one cell of memory right then how cam we use that formulae

 

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Why was the Access Time of L1 not added twice? (one for read, then later for write)

Answer 2

scene 1

• L2 block size is 16 words
• Data width between l2 and Main Memory is 4 words
  $\Rightarrow$ We need 4 access to Read from Memory and 4 access to store to L2
   To Read from MM require 200ns and To Store in L2 require 20 ns
   Total Time spent : 220 ns

scene 2

• stored information from L2 is read and stored on L1
•  Read from L2 takes 20ns and store on L1 takes 2 ns
   $\Rightarrow$  Total time spent in scene - 2 is  22ns

scene 1 and scene 2 can occur simultaneously which is depicted in the following figure

So , Total time spent
(220 *4 ) + 22 = 902 ns

Comments

As in question it is asked that's y we need to transfer from l2 to l1

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@Gabbar ,

When L1 is 2 blocks then will we transfer 4B still  from l2 ? or is there any ways we can transfer 2Blocks alone ?

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@pc sir great explanation ,,,sir you remove lots of doubts regarding these types of questions

Answer 3

answer is 902.

Comments

@skeltro Any Reference for this formula?

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Can you provide a source, please?

Answer 4

The size to transfer a block is always decided by source(Do not confuse yourself by looking "a block is transferred from L2 cache to L1 cache). In this case first 16 words will be transferred from main memory to L2 cache( IF nothing is mentioned, the last level cache L2 & main memory page size considered to be equal.) then only 4 words will be transferred from L2 to L1 not the whole block of L2. Now the only confusion is "This whole process of transferring block is a concurrent process or serial?".

If nothing is mentioned in the question then take serial transfer of block (in computer science we always strive for Worst case) so

1)   200ns to access main memory and 20ns to store in the L2 cache.

2)   Point (1) will happen for 4 times because of data bus = 4 words, so 16 words will be transferred in 4 times. 

3)   and after that 20ns to access or read L2 cache and 2ns to place or write it into L1 cache.

so answer would be

4*(200+20) + 20 + 2 = 902.

Comments

What will be the answer if the excecution is parallel? @Nitesh Singh 2

Answer 5

Miss in L1 cache and L2 cache results in the:

(200+20) for one word to get from main memory to l2 cache
(20+2) for one word to get from L2 cache to L1 cache

So total Time Needed is:   (200+20)*4  + (20+2)*4   = 968 

Comments

Transfer is done word by word or block by block ? Transfer time which is given for a block or for a word ?

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this answer i more correct as i also get the same answer and answer given on geeks for geeks is also 968

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I think It’ll be like this
(200+20) for 4 words to get from main memory to l2 cache..so for 16 words it’ll be 4*(200+20)

(20+2) for 4 words to get from L2 cache to L1 cache(Note:only the requested block will be sent from L2 to L1.)

So total Time Needed is: 4*(200+20)+(20+2)=902ns

Answer 6

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Comments

better answer

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When there is a miss in both $L1$ cache and $L2$ cache, first a block is transferred from main memory to $L2$ cache, and then a block is transferred from $L2$ cache to $L1$ cache. What is the total time taken for these transfers?

The question I feel like just wants to find the transfer time of the process undertaken once these miss happens (But then the question is so ambiguous)...Many of the top answers are including the time to store as well(which again is not given), Just giving the hint that store requires time would have removed lots of confusion