The full adder of the given figure receives two external inputs, x and y. The third input, z comes from the output of the D flip-flop. The carry output is transferred to the flip-flop every clock cycle. The external output ‘S’ gives the sum. Obtain the state table and state diagram of the sequential circuit (Figure is given below):

Question

Answer 1

To solve this problem, we need to analyze the behavior of the full-adder and the D flip-flop in a sequential circuit. Here’s a step-by-step breakdown:

Step 1: Understand the Components

• Full-Adder: Takes three inputs (x, y, z) and produces two outputs: sum (S) and carry (C).
• D Flip-Flop: Stores the carry output (C) and outputs it as z in the next clock cycle.

Step 2: Define the Full-Adder Truth Table

The full-adder truth table for inputs x, y, and z is:

x	y	z	S	C
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Step 3: Incorporate the D Flip-Flop

• The carry output (C) is stored in the D flip-flop and becomes the input z in the next clock cycle.

Step 4: Construct the State Table

The state table will include the current state (z) and the next state (z_next) based on the carry output (C).

x	y	z(current)	S	C	z_next (next state)
0	0	0	0	0	0
0	0	1	1	0	0
0	1	0	1	0	0
0	1	1	0	1	1
1	0	0	1	0	0
1	0	1	0	1	1
1	1	0	0	1	1
1	1	1	1	1	1

Step 5: Draw the State Diagram

The state diagram will represent the transitions between states (z) based on inputs x and y.

• State 0 (z = 0):

  • Transitions:
    • (x=0, y=0) -> State 0 (S=0, C=0)
    • (x=0, y=1) -> State 0 (S=1, C=0)
    • (x=1, y=0) -> State 0 (S=1, C=0)
    • (x=1, y=1) -> State 1 (S=0, C=1)

• State 1 (z = 1):

  • Transitions:
    • (x=0, y=0) -> State 0 (S=1, C=0)
    • (x=0, y=1) -> State 1 (S=0, C=1)
    • (x=1, y=0) -> State 1 (S=0, C=1)
    • (x=1, y=1) -> State 1 (S=1, C=1)

Final Answer

The state table and state diagram describe the sequential behavior of the full-adder with the D flip-flop. The state transitions are based on the carry output (C) being stored in the flip-flop and used as the input z in the next clock cycle.