Consider a system with a $4\,\text{KB}$ direct-mapped data cache with a block size of $16\,\text{bytes}$. The system is byte addressable and has a physical address space of $16\,\text{MB}$. During the execution of a program, four data words $P, Q, R,$ and $S$ are accessed in that order $16$ times (i.e., $PQRS\,PQRS\,\ldots$). Hence, there are $64$ accesses to the data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The byte addresses of the first bytes of $P, Q, R,$ and $S$ are $\text{0x845B32}$, $\text{0x845B26}$, $\text{0x845B36}$, and $\text{0x846B32}$, respectively.
For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
- Every access to $P$ is a miss.
- Every access to $R$ is a hit.
- Except for the first time, all subsequent accesses to $S$ are hits.
- Every access to $Q$ is a miss.
