Cache Memory

Question

$
\begin{array}{l}
\textbf{Q. } \text{A processor has the cache hierarchy as given. Assume that 20\% of instructions are}\\
\text{load/store instructions. The remaining 80\% are instruction-fetch accesses. Every L1 miss}\\
\text{accesses L2. Every L2 miss accesses main memory. Ignore all other overheads. IL1 and DIL1}\\
\text{are separate L1 caches. UL2 is a unified L2 cache shared by instructions and data.}\\
\text{Processor frequency}=2.5\,\text{GHz}. \text{ Assume that an L1 miss is followed by an L2 lookup.}
\end{array}
$

$$
\begin{array}{|c|c|c|}
\hline
\textbf{Level} & \textbf{Hit Time} & \textbf{Local Miss Rate}\\
\hline
\text{IL1 (Instruction L1)} & 1\text{ cycle} & 10\%\\
\hline
\text{DL1 (Data L1)} & 2\text{ cycles} & 5\%\\
\hline
\text{UL2 (Unified L2)} & 25\text{ cycles} & 2\%\\
\hline
\text{Main Memory} & 120\text{ cycles} & -\\
\hline
\end{array}
$$

$
\begin{aligned}
\text{i) }&\text{Find the AMAT (Average Memory Access Time) in cycles.}\\
\text{ii) }&\text{Find the global miss rate of UL2.}\\
\text{iii) }&\text{Find the effective memory access time in nanoseconds.}
\end{aligned}
$
$
\begin{array}{ll}
\text{A)} & 3.6,\;0.18,\;1.97\\
\text{B)} & 2.6,\;0.28,\;1.47\\
\text{C)} & 3.6,\;0.18,\;1.47\\
\text{D)} & 2.6,\;0.28,\;1.97
\end{array}
$

Answer 1

Given:

• IL1 hit time = 1 cycle, miss rate = 10%
• DL1 hit time = 2 cycles, miss rate = 5%
• UL2 hit time = 25 cycles, miss rate = 2%
• Main memory access time = 120 cycles
• 80% accesses are instruction fetches
• 20% accesses are load/store operations
• Processor frequency = 2.5 GHz

---

i) AMAT

For instruction-fetch accesses(80%):

\[

T_I = 1 + 0.10(25 + 0.02 \times 120)

\]

\[

= 1 + 0.10(25 + 2.4)

\]

\[

= 1 + 2.74 = 3.74 \text{ cycles}

\]

For data accesses(20%):

\[

T_D = 2 + 0.05(25 + 0.02 \times 120)

\]

\[

= 2 + 0.05(27.4)

\]

\[

= 2 + 1.37 = 3.37 \text{ cycles}

\]

Overall AMAT:

\[

AMAT = 0.8(3.74) + 0.2(3.37)

\]

\[

= 2.992 + 0.674

\]

\[

\boxed{AMAT = 3.666 \approx 3.67 \text{ cycles}}

\]

The option mentions 3.6 cycles.

---

ii) Global miss rate of UL2

First, calculate the fraction of all accesses that reach UL2.

\[

\text{L1 global miss rate}

= 0.8(0.10) + 0.2(0.05)

\]

\[

= 0.08 + 0.01 = 0.09

\]

Thus, 9% of all memory accesses reach UL2.

UL2 local miss rate = 2%.

Therefore,

\[

\text{Global UL2 miss rate}

= 0.09 \times 0.02

\]

\[

= 0.0018 = \boxed{i.e. 0.18\%}

\]

---

iii) Effective memory access time in nanoseconds

Processor frequency:

\[

2.5\text{ GHz}

\]

Therefore, clock cycle time is:

\[

\frac{1}{2.5\times10^9}

=0.4\text{ ns}

\]

Hence,

\[

\text{Effective access time}

=3.666\times0.4

\]

\[

=1.4664\text{ ns}

\]

\[

\boxed{\approx 1.47\text{ ns}}

\]

---

And that's why the final answer is: C) 3.6, 0.18, 1.47