Lets see the number of blocks in main memory and no. of sets in cache first, because consecutive blocks goes to different sets.
Block size = 64 words
Main memory size = 1M words
Cache size = 4K words, but being 4-way associative (4 blocks per set) we have 4K/(4*64) = 16 sets.
Now, for the given program processor fetches 4352 unique words from adjacent memory addresses. This corresponds to 4352/64 = 68 unique blocks.
So, all these unique block accesses are definitely cache misses (cache is initially empty). So, our cache hit rate
$= \frac{4352-68}{4352}=98.4375\%$
Now, are all these compusory misses - yes, because they are all first accesses to a block.
So, no. of compulsory misses = 68.
Since no. of compulsory misses = total no. of misses, this means no. of conflict misses = 0.
Conflict misses are those which could have been avoided with a fully associative cache and LRU replacement policy
Here, no block is accessed more than once and hence no chance of conflict miss. For same reason capacity miss is also not there. Only thing is we have block replacements in cache and this amounts to 4.
| |
Col 1 |
Col 2 |
Col 3 |
Col 4 |
| Set 1 |
0-63 |
1024-1087 |
2048-2111 |
3072-3135 |
| Set 2 |
64-127 |
.. |
.. |
.. |
| Set 3 |
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| Set 4 |
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| Set 5 |
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| Set 6 |
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| Set 7 |
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| Set 8 |
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| Set 9 |
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| Set 10 |
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| Set 11 |
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| Set 12 |
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| Set 13 |
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| Set 14 |
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| Set 15 |
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| Set 16 |
960-1023 |
.. |
.. |
4032-4095 |
Now, we have 4 more blocks left. And these will be replacing the Col 1 entries of sets 1-4. But these are clearly compulsory misses. Suppose these replaced ones were again accesses and miss happened, then they would have been capacity misses - if the miss would have happened even with full associativity and LRU replacement, then they would be counted as capacity misses. Well, this question is so simple - 0 can be told even without thinking anything.
