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Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 20% of the time for 1 cycle and 5% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI?
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Pipeline stalls are introduced in the pipelines architecture, so CPI will increase

Stalls per instruction $ = 0.2 \times 1$ cycle $+ 0.05 \times 2$ cycle = 0.3

New CPI = old CPI + stalls per cycle = 1.4 + 0.3 = 1.7

so, Pipelined architecture will have CPI of 1.7

Refference : https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf Q. 4.4

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3 votes

Unless and until mentioned ,

CPIideal pipeline(without stalls)  =  1

The given CPI of 1.4 is for non pipelined processor not the pipelined one..So it would be wrong to consider it for pipelined system..

Now we calculate no of stall cycles / instruction = 0.2 * 1 + 0.05 * 2

                                                                      = 0.3

So CPI for the modified pipelined system i.e. with stalls  =  1 + 0.3

                                                                                   =  1.3

Hence the correct answer should be 1.3

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