Pipelining and CPI

Question

Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 20% of the time for 1 cycle and 5% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI?

Answer 1

Pipeline stalls are introduced in the pipelines architecture, so CPI will increase

Stalls per instruction $ = 0.2 \times 1$ cycle $+ 0.05 \times 2$ cycle = 0.3

New CPI = old CPI + stalls per cycle = 1.4 + 0.3 = 1.7

so, Pipelined architecture will have CPI of 1.7

Refference : https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf Q. 4.4

Comments

Plz have a look at my answer @Lokesh Dafale..

Answer 2

Unless and until mentioned ,

CPI_{ideal pipeline(without stalls)}  =  1

The given CPI of 1.4 is for non pipelined processor not the pipelined one..So it would be wrong to consider it for pipelined system..

Now we calculate no of stall cycles / instruction = 0.2 * 1 + 0.05 * 2

                                                                      = 0.3

So CPI for the modified pipelined system i.e. with stalls  =  1 + 0.3

                                                                                   =  1.3

Hence the correct answer should be 1.3

Comments

but it conflicts with the following staement

Pipelining doesn't reduce the time it takes to complete an instruction

 we can only reduce the average time to complete an instruction because more than one instructions are in execution 

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If we talk about a single instruction then it is true but we are considering average CPI right so we should consider for every instruction..

Hence we are doing like that..

This can also be verified by  speedup factor..

 In ur case it will be less than 1(1.4/1.7) which is undesirable for pipelined system..

In my case it is coming to be 1.4/1.3 which is greater than 1..

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speed up factor $ = \frac{CPI(nonpipeline) \times Clock\_cycle(nonpipeline)}{CPI(pipeline) \times Clock\_cycle(pipeline)} = \frac{1.4 \times 10}{1.7 \times y}$

here y= clock cycle in pipeline which is max{t1, t2,...tk} for k stages

and you are assuming y=10ns and I think this cant be true

in my case speedup to be 1 y should be 8.23
in your case speedup to be 1 y should be 10.76(which is even greater than non pipeline clock cycle)

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But stage delay is not mentioned right??

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its not mentioned but you have to assume it less than 10 or else that pipeline will be useless

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@Lokesh. Why assume? Lets say there are 'n' stages so that stage delay is

(10ns * $\frac{1.4}{n}$) = $\frac{14}{n}$

Now, speedup = numerator/denominator

where, numertor = 1.4 * 10 =14

and denominator = 1.7 * $\frac{14}{n}$

Thus, speedup = $\frac{n}{1.7}$

Now, as they have given register delay, there must be atleast 2 stages i.e. n>=2 else there is no meaning to pipelining.

So, min. speedup = $\frac{2}{1.7}$

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see the link in above ans ...it says ques is ambiguous you can solve it by both methods

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@Lokesh. You meanif stage delays arent given, we are free to assume new CPI , right?

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if stalls are not given then assume ideal CPI = 1

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@Lokesh. Didnt get you.

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with out stalls CPI =1
with stalls CPI = 1+stalls

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@lokesh. Thanks

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@habib so 20ps information are worthless??

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Here we need to find only CPI..Hence no need to think about the delays in this question..

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The question is not even copied properly, why argue over it then?