Anti Dependence =============== Write After Read Dependencies
S1 I2: MUL R7, R1, R3
I5: MUL R7, R8, R9
in this there is Write After Write dependencies Also called Output Dependencies
So, s1 is false
S2 I2: MUL R7, R1, R3
I4: ADD R3, R2, R4
there is case in which R3 is written First By I4
and then after R3 is read by I2 which is wrong thats why it is Write after Read Dependencies
so, S2 is True
S3 is wrong Because Anti-dependence can be overcome in pipeline using register renaming.