1,441 views
1 1 vote
consider a 32 bit microprocessor which has 32K byte which is 4-way set associative cache.Block size of cache is 2 32-bit words.The set number to which wprd from memory location FAFEEBE1 wrapped ___.

I'm confused about 2 32-bit words as block size .Answer given was based on <Tag,Set,Word> =<19,9,4>

1 Answer

Best answer
1 1 vote

physical address

29 3

no of sets = n/ assocoativity 
        n= cache size/block size 
          =32Kbyte/23

            =215 / 23 =212

     no of sets = 212 /22

                              = 210 

   set bits = 10 

19 TAG 10 set 3 block offset

1111 1010 1111 1110 1110 1011 1110 0001

blue color marked will give hexa decimal as : 0001 0111 1100

                                                                        : 17C (ANSWER)

• selected by
Position:
Show:

Related questions

1 1 vote
1 1 answer
908
908 views
kimaya asked Jul 8, 2017
908 views
The answer in the solution is b. My confusion is that adding word to a block will reduce Miss Rate and not Miss Penalty. So shouldn't the answer be c, i.e. only S2 is cor...
1 1 vote
2 answers 2 answers
2.7k
2.7k views
saurav04 asked Nov 28, 2015
2,651 views
During a program execution out of 1000 memory references there are 250 and 120 misses in L1 (Level1) and L2(Level2) caches respectively. Hit times for L1 and L2 cache are...
1 1 vote
2 2 answers
901
901 views
1 1 vote
0 0 answers
1.8k
1.8k views
atulcse asked Jan 13, 2022
1,782 views
Consider a 4-way set associative cache of 64 KB used in a 32-bit CPU, organized into 32-word blocks. System supports 64 GB RAM. Cache is designed with a write back protoc...