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*Basics required*:

2-Memory addressing and languages

3-software and architecture types( watch from 14:26 seconds )

4-Instruction Set architecture

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Data Dependence and Data/Control Hazards Video

Adding the corrected pipeline diagram for the question discussed in the video:

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A CPU uses two levels of caches L1 and L2. It executes two types of

jobs J1 and J2. Their details are as follows:

(A) J1 comes with a probability of 0:3 and requires 2000 memory references,

all for reading. For J1, there are 100 misses in L1 and 60

misses in L2.

(B) J2 comes with a probability of 0:7 and requires 3000 memory references,

all for reading. For J2, there are 50 misses in L1 and 70

misses in L2

The L1 hit time is 2 cycles and the L2 hit time is 10 cycles. The L2 miss

penalty is 200 cycles. What is the average memory access time?

Please Sir help me with this .. I am really...

jobs J1 and J2. Their details are as follows:

(A) J1 comes with a probability of 0:3 and requires 2000 memory references,

all for reading. For J1, there are 100 misses in L1 and 60

misses in L2.

(B) J2 comes with a probability of 0:7 and requires 3000 memory references,

all for reading. For J2, there are 50 misses in L1 and 70

misses in L2

The L1 hit time is 2 cycles and the L2 hit time is 10 cycles. The L2 miss

penalty is 200 cycles. What is the average memory access time?

Please Sir help me with this .. I am really...

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**Important Ones**

http://gateoverflow.in/questions/co-and-architecture?sort=featured

**Difficult Ones**

**http://gateoverflow.in/8560/gate2015-3_51**** **Question regarding Minimum Average Latency from Dynamic Pipeline portion asked once in 2015.

**Extra Questions **

To see more, click for the full list of questions or popular tags.