Recent posts in CO & Architecture

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Most people have trouble with Cache Misses. You can go through this:

https://gatecse.in/cache-misses/

Arjun posted in CO & Architecture Jan 28, 2019
by Arjun
1,062 views
3

Introduction Slides

Data Dependence and Data/Control Hazards Video 

Reference Slides

Adding the corrected pipeline diagram for the question discussed in the video:

 

Arjun posted in CO & Architecture Jan 27, 2019 edited Jan 28, 2019 by Arjun
by Arjun
2,893 views
4
A CPU uses two levels of caches L1 and L2. It executes two types of
jobs J1 and J2. Their details are as follows:
(A) J1 comes with a probability of 0:3 and requires 2000 memory references,
all for reading. For J1, there are 100 misses in L1 and 60
misses in L2.
(B) J2 comes with a probability of 0:7 and requires 3000 memory references,
all for reading. For J2, there are 50 misses in L1 and 70
misses in L2
The L1 hit time is 2 cycles and the L2 hit time is 10 cycles. The L2 miss
penalty is 200 cycles. What is the average memory access time?

 

Please Sir help me with this .. I am really...
Payel posted in CO & Architecture May 2, 2016
by Payel
547 views
5

Important Ones

http://gateoverflow.in/questions/co-and-architecture?sort=featured

 

Difficult Ones

http://gateoverflow.in/8560/gate2015-3_51   Question regarding Minimum Average Latency from Dynamic Pipeline portion asked once in 2015.

 

Extra Questions 

Arjun posted in CO & Architecture Aug 4, 2015 edited Feb 2 by Arjun
by Arjun
4,299 views
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