Data Dependence and Data/Control Hazards Video
Adding the corrected pipeline diagram for the question discussed in the video:
@Arjun Sir, you said in video that in True dependency consider the previous write only. I want to confirm that in Anti dependency and Output dependency can we consider out of order dependency?
@Arjun Sir, Please answer the above query. Please check is my understanding right?
R4 <- R1 + R4
R4 <- R2 + R4
R4 <- R4 + R5
there are following dependencies-
1) RAW(True) - (I1-I2) , (I2-I3) we'll not count (I1-I3) so 2.
2) WAR(Anti)- (I1-I2),(I1-I3) and(I2-I3) so 3.
3) WAW(Output) - (I1-I2),(I2-I3) and (I1-I3) so 3.
in the video you told that WAR and WAW hazards cannot happen in an inorder pipeline..But in this link https://people.engr.ncsu.edu/efg/521/s06/common/lectures/notes/lec18.pdf
It is shown that WAR and WAW hazards can happen in an inorder pipeline also..where am I missing out?Can you pls explain Sir?
@Arjun Sir, if there is no data forwarding, why is the decode stage in I2 before WB in I1? (Same with decode in I4 before WB in I3). Won't the register files get old data in the decode stage? And if so, then how EX stage is getting the new if no forwarding is there?
@MiNiPanda, that is because of split phasing WB writes in first half cycle & ID reads operands in 2nd half of a clock cycle.
@Shubhgupta Okay so we can consider split phase at all times even if its not mentioned right? Thank you!! :)
Can you clear me one more thing.. why there is a RAW hazard b/w I2 and I4? I4 anyway have to wait for I3. So I2 isn't causing any extra stall.
Please check my comment again. I have edited it.