The Gateway to Computer Science Excellence

Introduction Slides

Data Dependence and Data/Control Hazards Video 

Reference Slides

Adding the corrected pipeline diagram for the question discussed in the video:


posted Jan 27 in CO & Architecture by Veteran (421,927 points)
edited Jan 28 by | 1,346 views


video link is not working Sir.
Fixed now

@Arjun Sir, you said in video that in True dependency consider the previous write only. I want to confirm that in Anti dependency and Output dependency can we consider out of order dependency? 

@Arjun Sir, Please answer the above query. Please check is my understanding right?

R4 <- R1 + R4

R4 <- R2 + R4

R4 <- R4 + R5 

there are following dependencies-

1) RAW(True) - (I1-I2) , (I2-I3) we'll not count (I1-I3) so 2.

2) WAR(Anti)- (I1-I2),(I1-I3) and(I2-I3) so 3.

3) WAW(Output) - (I1-I2),(I2-I3) and (I1-I3) so 3. 


there is dependency but it is not causing hazards
@Shubh+Gupta Yes. For WAW and WAR the dependency come to play only when instruction reordering happens.

For RAW dependency as per Bernstein's condition I1-I3 is also a dependency. But in none of the standard references nor dependency outputting software that is output and so you should not count it in GATE also.

@Arjun Sir

in the video you told that WAR and WAW hazards cannot happen in an inorder pipeline..But in this link

It is shown that WAR and WAW hazards can happen in an inorder pipeline also..where am I missing out?Can you pls explain Sir?

In the slide it is mentioned rt -- either instruction reordering or newer instruction jumping ahead to a stage before older one -- this won't happen in classical RISC pipeline.
Got it Sir..thanks! :)

@Arjun Sir, if there is no data forwarding, why is the decode stage in I2 before WB in I1? (Same with decode in I4 before WB in I3). Won't the register files get old data in the decode stage? And if so, then how EX stage is getting the new if no forwarding is there?

Please help

@MiNiPandathat is because of split phasing WB writes in first half cycle & ID reads operands in 2nd half of a clock cycle.

@Shubhgupta Okay so we can consider split phase at all times even if its not mentioned right? Thank you!! :)

Can you clear me one more thing.. why there is a RAW hazard b/w I2 and I4? I4 anyway have to wait for I3. So I2 isn't causing any extra stall.

yes we need to always consider the best case. according to all previous gate questions they are using split phase in question if mentioned or not mentioned.


Please check my comment again. I have edited it.

at first I also thought this question but think if I3 is not present in pipeline then I4 needs to wait till I2 writes back so this will cause stall in pipeline in finding of hazard we consider all those dependency which cause stall in pipeline not those which consider extra stall. So at 7th clock both I2 and I3 causing stall in pipeline.
Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,662 questions
56,122 answers
93,029 users