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Recent questions tagged gatecse2024-set2
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GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$ ... the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instruc...
Arjun
1.9k
views
Arjun
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Feb 16
CO and Architecture
gatecse2024-set2
numerical-answers
co-and-architecture
instruction-format
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–
1
votes
3
answers
62
GATE CSE 2024 | Set 2 | Question: 52
Let $L_{1}$ be the language represented by the regular expression $b^{*} a b^{*}\left(a b^{*} a b^{*}\right)^{*}$ and $L_{2}=\left\{w \in(a+b)^{*}|| w \mid \leq 4\right\}$, where $|w|$ denotes the length of string $w$. The number of strings in $L_{2}$ which are also in $L_{1}$ is _________.
Let $L_{1}$ be the language represented by the regular expression $b^{*} a b^{*}\left(a b^{*} a b^{*}\right)^{*}$ and $L_{2}=\left\{w \in(a+b)^{*}|| w \mid \leq 4\right\}...
Arjun
2.3k
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Arjun
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Feb 16
Theory of Computation
gatecse2024-set2
numerical-answers
theory-of-computation
regular-expression
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2
votes
2
answers
63
GATE CSE 2024 | Set 2 | Question: 53
Let $Z_{n}$ be the group of integers $\{0,1,2, \ldots, n-1\}$ with addition modulo $n$ as the group operation. The number of elements in the group $Z_{2} \times Z_{3} \times Z_{4}$ that are their own inverses is ___________.
Let $Z_{n}$ be the group of integers $\{0,1,2, \ldots, n-1\}$ with addition modulo $n$ as the group operation. The number of elements in the group $Z_{2} \times Z_{3} \ti...
Arjun
2.3k
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Arjun
asked
Feb 16
Set Theory & Algebra
gatecse2024-set2
numerical-answers
set-theory&algebra
group-theory
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6
votes
2
answers
64
GATE CSE 2024 | Set 2 | Question: 54
Consider a $32$-bit system with $4 \mathrm{~KB}$ page size and page table entries of size $4$ bytes each. Assume $1 \mathrm{~KB}=2^{10}$ bytes. The OS uses a $2$-level page table for memory management, with the page table containing ... the maximum number of pages across the two levels of the page table of the process. The value of $\text{X+Y}$ is ___________.
Consider a $32$-bit system with $4 \mathrm{~KB}$ page size and page table entries of size $4$ bytes each. Assume $1 \mathrm{~KB}=2^{10}$ bytes. The OS uses a $2$-level pa...
Arjun
3.3k
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Arjun
asked
Feb 16
Operating System
gatecse2024-set2
numerical-answers
operating-system
virtual-memory
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2
votes
1
answer
65
GATE CSE 2024 | Set 2 | Question: 55
Consider the following augmented grammar, which is to be parsed with a $\text{SLR}$ parser. The set of terminals is $\{a, b, c, d, \#, @\}$ \[ \begin{array}{l} S^{\prime} \rightarrow S \\ S \rightarrow S S|A a| b A c|B c| b ... $\operatorname{GOTO}\left(I_{0}, S\right)$ is __________.
Consider the following augmented grammar, which is to be parsed with a $\text{SLR}$ parser. The set of terminals is $\{a, b, c, d, \#, @\}$\[\begin{array}{l}S^{\prime} \r...
Arjun
2.7k
views
Arjun
asked
Feb 16
Compiler Design
gatecse2024-set2
numerical-answers
compiler-design
lr-parser
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