Instruction format

Question

Consider a hypothetical 32 bit microprocessor having 32 bit instructions composed of two fields: The first 4 bits contains the opcode and the remainder an immediate operand, an operand address, or register references.

a. What is the maximum directly addressable in bytes.
b. What is the impact on system speed if the microprocessor bus has:

1. a 32 bit local address bus and a 16 bit local data bus?
2. a 16 bit local address bus and a 16 bit local data bus?

c. Is this machine more likely to be a RISC or CISC architecture ?

Answer 1

a. Out of 32 bit instruction, 4 bit is opcode. So, remaining 28 bits can be used as an operand address and hence up to $2^{28}$ bytes can be addressed assuming byte addressing. 

b. 

1. 32 bit address bit means full capability of $2^{28}$ addresses can be used. But 16 bit data width means each instruction requires two memory reads.
2. With 16 bit address field we can address only $2^{16}$ words of memory. So, two memory reads are required for each address using address latching which slows down the microprocessor. Here also, two memory reads are required for each instruction as we have only 16 bit data bus.

c. It is more likely to be a RISC machine as we are having maximum $2^4 = 16$ instructions only.