2 votes 2 votes here what about WB---> ID (operand forwarding) ?? i think this one have no meaning??? CO and Architecture made-easy-test-series co-and-architecture pipelining + – Hradesh patel asked Jan 12, 2017 • edited Mar 7, 2019 by adeebafatima1 Hradesh patel 731 views answer comment Share Follow See all 7 Comments See all 7 7 Comments reply vijaycs commented Jan 13, 2017 reply Follow Share yes ...ambiguity is there in operand forwarding from PO to ID stage ..but forwarding from WB to ID is making it clear that we can can execute PO and ID in the same cycle and same with WB to ID... otherwise it has no meaning in saying forwarding from WB to ID. See this - similar question.--https://gateoverflow.in/8218/gate2015-2_44 And ans should be, no of stalls = 4. // 2 during I4 and 2 during I2 and I3 in 4th cycle. 0 votes 0 votes Sushant Gokhale commented Jan 13, 2017 reply Follow Share @Vijay. First, I couldnt find any ambiguity. Second, they have asked maximum stalls in any single instruction ? So, could you check my answer? Should we consider the stalls before IF in 5th instruction? If yes, 4 is right answer else 2 is right answer. 0 votes 0 votes Sushant Gokhale commented Jan 13, 2017 reply Follow Share @Vijay. Got the ambiguity. Have posted the answer with and without split phase. But with split phase, getting 2 stall cycles. 1 votes 1 votes Hradesh patel commented Jan 13, 2017 reply Follow Share they give a solution plz check ininstruction I2 its say no stall but here I2-I0 is WB- ID so here i got 1 stall same as @vijaycs diagram so i am get total 4 stall . and in I5 ---> 2 stall,.but i think the ambiguity that the ask total or maximum stall of any instruction???? @ Sushant Gokhale 0 votes 0 votes Sushant Gokhale commented Jan 13, 2017 reply Follow Share @Hradesh. There shouldnt be any stall in I2 because ID of I2 will get R2 from I0 at start of cycle. So, no issues. So, above diagram is perfect. They are asking max stalls in any of the instructions. 0 votes 0 votes Sushant Gokhale commented Jan 13, 2017 reply Follow Share So, without split phase, its 4 cycles With split phase, its 2 cycles. 0 votes 0 votes vijaycs commented Jan 13, 2017 reply Follow Share @Hardesh , Yes ans should be 2 according to the question..as it is asking for maxmum stalls of any instruction...if it was total stalls in execution of all 5 instructions then ans would have been more than or equal ( if no stalls in othe instruction) to 2 but here I have doubt in total stalls ..because they are saying only 2 but what about I0-I2 ( r2 ) and I2- I4 (r0) data dependency.. ..how these two are not causing any stalls... @Sushant's logic also seems correct to me... @Kapil, @Arjun sir ..can you please see this .. 0 votes 0 votes Please log in or register to add a comment.
3 votes 3 votes Following is how the execution will take place without split phase between PO-ID: Note: Blue cells indicate stalls. With split phase between PO-ID, following is the execution pattern: Sushant Gokhale answered Jan 13, 2017 • edited Jan 13, 2017 by Sushant Gokhale Sushant Gokhale comment Share Follow See all 8 Comments See all 8 8 Comments reply Show 5 previous comments Sushant Gokhale commented Jan 13, 2017 reply Follow Share @Vijay PO buffer is modified at the end of 4th cycle. But if we do forwarding from PO of I0 to ID of I3, ID of I3 will get the correct data even before the 4th cycle has started or at the start of 4th cycle. 0 votes 0 votes vijaycs commented Jan 13, 2017 reply Follow Share ^yes, looking fine ... : ) Now lets wait for any experts for confirmation.. 1 votes 1 votes Kapil commented Jan 13, 2017 reply Follow Share @sushant, its fine !! 1 votes 1 votes Please log in or register to add a comment.