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Pipelining

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Consider a non-pipelined processor design with clock cycle time zones and average CPI 1.5. Now it is decided to shift pipeline processor, it has 5 stages taking 2ns, 3ns, 5ns, 3ns time, each stage also adds 20ps due to register setup delay. The pipeline stalls 20% of time for 1 cycle and 10% of time for 2 cycles. Then what is the new CPI the pipelined processor ?

Correct Answer: 1.9    Status: unattempted

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