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Consider a computer with the following features:

90% of all memory accesses are found in the cache (hit ratio = 0.9);
The block size is 2 words and the whole block is read on any miss;
The CPU sends references to the cache at the rate of 107 words per second;
25% of the above references are writes (writes = 25%, reads = 75%);
The bus can support 107 words per second, read or writes (total bus bandwidth = 107);
The bus reads or writes a single word at a time;
Assume at any one time, 30% of the block frames in the cache have been modified;
The cache uses write allocate on a write miss.

Calculate the percentage of the bus bandwidth used on the average if cache is WRITE BACK:

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WRITE BACK = When cached data is modified, it is just marked using dirty bit. The original data is updated when the cached data is deallocated.

and

Write Allocate – If a write miss occur, load the block into cache and then update. Write back policy generally uses this.

Consider the scenarios for using  bandwidth

  1. Read hit: While Read hit, block is present in cache, so no usage of bandwidth
  2. Read miss: We must write back the block is dirty, then load new block. Probability of read miss= (1-0.9)*0.75; Replacing the dirty block =0.3* one block =0.3*2 words
  3. Write hit= As block is not updated in main memory immediately, no bandwidth use
  4. Write miss= 107 * 0.1 * 0.25 * [2 * 0.3 + 2]

Percentage of the bus bandwidth used = sum of these/total =0.26 * 10 7 /10 7 =0.26

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