Consider a system with 64KB cache and line size of 32 bytes. The cache will allocate a line on write miss. Assume cache is connected to lower level memory in the hierarchy through a 64-bit wide bus. The number of CPU cycles for a B-bytes write access on this bus is 10+5((B/4)-1).
Consider below C code snippet :
#define PORTION 1
Base = 8 * i;
for (unsigned int j = base; j < base + PORTION; j++)
Data[j] = j; // storing j into memory
Assume j is stored in register and unsigned int size 32 bits.
1. For write through cache, how many CPU cycles are spent on write transfers to the memory for the all the combined iterations of the j loop in the above C code snippet?
2. If the cache is configured as write back cache, how many CPU cycles are spent on a write back a cache line?
