(C) is the correct answer!
$Remark:$
1. If $clear = 1$, counter will be reset to 0000 $\underline{\text{without any delay, and counter doesn't count 5}}$.
2. If $load=1$, counter will be loaded with the input 0011, but note that $\underline{\text{counter counts 5 in this case}}$ unlike clear input.
3. Counter counts from $0$ to $4$.
4. Clear and Load are direct inputs, it means they can be applied to the counter without using any pulse.
When the output reaches the count of 1001, both A0 and A3 become 1, making the output of the AND gate equal to 1. This condition activates the Load input; therefore, on the next clock edge the register does not count, but is loaded from its four inputs. Since all four inputs are connected to logic 0, an all‐0’s value is loaded into the register following the count of 1001. Thus, the circuit goes through the count from 0000 through 1001 and back to 0000, as is required in a BCD counter.
In Fig (b), the NAND gate detects the count of 1010, but as soon as this count occurs the register is cleared. The count 1010 has no chance of staying on for any appreciable time, because the register goes immediately to 0.
- If $clear=1$, then clear the counter.
- If $clear=0, load = 0, count = 1,$ counter counts.
- $load = 1,$ loads the input to the counter.
If $load = 1$, then counter will be loaded with $i/p = 0011$
to the given counter, $count = 1, load = 0, clock = \uparrow$
$\underline{\text{Note:}}$ If o/p of $\textsf{AND}$ gate is led to $load$, then counter will be loaded with $0011$.