GATE CSE 2005 | Question: 19

Question

 Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

• A. Neither vectored interrupt nor multiple interrupting devices are possible

• B. Vectored interrupts are not possible but multiple interrupting devices are  possible

• C. Vectored interrupts and multiple interrupting devices are both possible

• D. Vectored interrupts are possible but multiple interrupting devices are not possible

Comments

Answer is Option C.

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I guess people are confused that “there will be no address bus from I/o to transfer addresses”

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Here ans is C..

 Explanation : Cpu has single interrupt req line so Other IO devices Interrupt line is connected via OR gate to the cpu req line.. Where the output of the OR gate is connected to the Cpu req line.. And IO devices interrupt pins is going as a input to the OR gate... So in this way Cpu got to know.. That some IO need attention.. But Questions is How cpu will know.. Who is interrupted.. Here the ans..

After completing it's current instruction.. cpu check it's INTR (Interrupt Request) pin if it is 1..then..it Set INTA (Interrupt Acknowledge) pin = 1 which is connected to the highest priority IO.. Here the IO devices is placed according to their priority.. Means highest priority device is closest to the CPU.. Then one after another according to their priority.. So.. When the acknowledge signal goes to 1st IO device.. If it interrupted then it send it's Vector number via data bus to the cpu.. Then cpu got the ISR address from Interrupt Vector Table.. Of the corresponding vector no.. And then interrupt is serviced... But if the 1st device is not interrupted.. Then the 1st IO device forward the Acknowledge signal to the next priority IO device... Then the prev process repeats...

So Vectored interrupts and Multiple Interrupting devices both are possible... When cpu has a single interrupt req line and a single grant line..

 

Answer 1

(C) is the correct answer. We can use one Interrupt line for all the devices connected and pass it through OR gate. On receiving by the CPU, it executes the corresponding ISR and after exec INTA is sent via one line. For Vectored Interrupts it is always possible if we implement in daisy chain mechanism.

Ref : Click Here 

Comments

what's the key in gate paper can anybody tell. Thanks in advance.

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I think, there were no official key back then.

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Gupta731 its in syllabus

Answer 2

Answer is C.
Both Vectored interrupts and multiple interrupting devices are both possible.

You know about parallel & serial connection(Daisy Chain).
Multiple devices are connected serially.

This is how it looks like.

So how it handles multiple interrupts ?
By the way what does it mean by handling multiple interrupts?
It means handling the interrupt from multiple I/O devices, & when two or more devices cause interrupt simultaneously, we want to give priority to High priority I/O.

The way it is implemented is....
Even if one I/O device caused interrupt, we can know it...   but who raised it ?
Interrupt ACK is connected to I/O1  (I/O with Highest priority)
If the interrupt was caused by I/O1 then, it will not forward the signal to I/O2. So we can know it was caused by I/O1.
If it was caused by I/O3, then I/O1 will forward it, I/O2 wil forward it .. So it is caused by I/O3.
So we are checking from highest priority I/O to lowest priority.
If two or more device cause interrupt, then priority will be given to higher priority since ACK moves from highest priority, so it will not forward ACK, & we can know we have to serve it first.

Comments

@rahul Sharma

When the device has raised an interrupt and INTA signal reaches it, then it stops the signal from going further. After this, it puts down the INTR signal and sends its vector code to the processor via the data bus.

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but how vectored interrupts are possible.

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No doubt. Ans is C.

But Daisy-Chaining Priority method used for serial connection of I/O devices.

For parallel I/O devices, Priority encoder (different MCU) is used. And it is called Parallel Priority Interrupt method.

You can read both methods in Morris Mano (Computer System Architecture) 3rd edition, p.no. 408-409.

Answer 3

C. is the right option.

Daisy chain can be used.

Comments

it is b)

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what's the correct answer at many place B option is given as the right answer.

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but answer is option B

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Which one is correct? why is C wrong?

Answer 4

Vectored Interrupts are those interrupts in which an I/O module places it's word(usually it's address or a unique service identifier) on the bus so that the cpu can recognize the respective I/O module.

Using, single interrupt request line and single interrupt grant line, both multiple interrupts and vectored interrupts are possible.

Example : Intel 80386 configured with External Interrupt Arbiter : Intel 82C59A

The below read may be further useful

Source : William Stallings 9ed

So ans- (c)

Answer 5

option c is correct …  for example daisy chainning there is only one interrupt request line and one interrupt grant lline

Answer 6

CPU has single interrupt request and grant line. Here multiple request can be given to CPU but CPU interrupts only for highest priority interrupt so option (A) & (D) are wrong. But here in case of single interrupt lines definitely vectored interrupts are not possible. Hence (B) is correct option.

Comments

correct answer should be (B)

we use daissy chain suct that multiple devices raise an interrupt and their interrupts are services in a chain one by one

but in vectorred interrupt, only high priority device are served and other requests are masked with the use of masking register such that no other low priority device can interrupt the current device operation