# GATE2005-70

16.8k views

Consider a disk drive with the following specifications:

$16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a $4$ byte word from the memory in each DMA cycle. Memory cycle time is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:

1. $10$
2. $25$
3. $40$
4. $50$

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4
Why people are not considering the number of surfaces when the data transfer rate being calculated??!!!
4
because we have only one head unless its clearly specified that there are multiple heads.
16
no that is not the reason,actually by default we have rd/wr head for every surface..but data transfer rate is measured for 1 track only
0
it's because all heads are identical and move at the same time, so they take exactly the data transfer time to transfer data across the disk to internal buffer
0
Why we are not considering 'Seek time' & 'Rotational Delay' also ??
0
but the amount of data transferred in that time varies...for example  according to you, in x sec, we can read all y surfaces having b bytes of data..so data transfer would be y*b/x but it is only y/x in the question...correct me if I am wrong?
0
What is the difference between the amount of cpu time consumed and the amount of time that the cpu gets blocked

$512$ KB-$1/50$  sec

$4$ Byte transfer will take total :$4/(512\times50\times2^{10})=152.58 \ ns$

DMA will transfer $4$B in $40$nsec

So, Cpu will be blocked $(40/152.58)=26 \%$ of time

edited
8
you should do 40 / ( 40 +152.58)  = 0.2077
25

@ashish

No, we should not add 40 again with 152.58 , it is 40/158.58 which is correct.

cycle stealing will be default pipelining as when first byte is getting transferred at the same time the device will keep on buffering the next byte ..so vacation of this 1 byte and accumulation of next 1 byte overlap and this cycle continues.

Reference:

https://gateoverflow.in/116524/coa-dma-doubt

0
@bikram sir,

as per the disk specification it will take 156.25ns to transfer 4Bytes.

in the given question , 4Bytes can be transferred in 1 DMA cycle...and 1 Memory cyle is 40ns..

What is the formula used here for % of time CPU get blocked? Also can we say 1 DMA cycle =156.25ns?
13
The disk is operated in cycle stealing mode mention explicitly .

In this case we use  ( x/y ) to calculate % of cpu time consumed/blocked .

Where , x=  Data preparation time or CPU time   and y=  Data transfer time
3
@Bikram sir, how the % of time CPU is blocked is Data preparation time / Data transfer time.
In Data preparation time CPU is not blocked, it has the buses with it, only in Data transfer time it is blocked from having the Buses.
So % time CPU is blocked should be Data Transfer time/ Data Preparation time.. ??
am I wrong ??
2

No you are not wrong .. i just use different convention here..

In my convention

X = preparation time is total cycle time,

Y = transfer time, that is data transfer time..

In general , device is slow as compare to CPU , it will generate data in slow speed , so device takes Long time to transfer data  .  That's why Transfer time will always greater than cycle time or data preparation time  .

that means Y > X

that's why we do X/Y

Denominator is always need to large than Numerator .

Hope now it is clear why X/Y formula is correct because Device is slower than CPU.

0
sir how are you saying device is slow ? disk transfer rate is 400 MBps means to transfer 4 byte word from io device its dma buffer 10ns are needed whereas CPU will need a memory cycle of 40ns. And 400 MBps transfer rate I am getting is by considering all surface accesses in parallel which is the default? is there any other thing to do with the transfer rate?
0
I said , in general , Device is obviously slower than CPU . Without the context of this particular question , don't you think CPU is a fastest device ?

although cpu is not idle during DMA, it can do other tasks which doesn't need memory.
2
@shivansh gupta
I think you'll agree on the fact that main memory is slower than the processor, right? yes. then Hard disk drive is much slower than Main memory. so CPU is faster than the Hard disk drive.

If you've seen CPU arc. in real then you must have seen CPU clock rate to be 2.3-4Ghz and the speed of its buses operate around 8GT/sec(gigatransfer/sec) and if you take the Hard disk, a better one that operates on 7200rpm then what speed you might get around may 120MB/s. I think CPU is pretty fast. [Numbers are not exact just for reference].

And regarding x and y. There are different convention possible.
Cpu will be ideal for (data transfer from DMA to memory or memory cycle time/time in which DMA fill in from disk).
0

@bhuv I am not saying that CPU speed is less that IO device speed. According to the specifications given in the question IO device transfers 4B data in 10ns whereas CPU takes 40ns due to bus limitations. If bus width or word size would have been more it would have taken more data in 10ns.

I am also saying the same thing as you have said

Cpu will be ideal for (data transfer from DMA to memory or memory cycle time/time in which DMA fill in from disk).

i also said the same thing in my comment above. I saw the opposite written in a comment thats why I asked.

Now according to this question, for 1 dma operation

data transfer time from dma to memory or memory cycle time = 40ns                                                               and time in which dma fill in from disk = 10ns  (dma gets 4B in 10ns and it has to transfer after getting 4B)

Now if I use this formula, the Numerator is more than denominator and it does not makes sense, this is what I was saying..

2

I saw the opposite written in a comment thats why I asked.

This is not written oppositely in my comment :D

i said

X = preparation time is total cycle time,

Y = transfer time, that is data transfer time..

and i did X/Y as Y > X .

You think

Y = preparation time is total cycle time,

X = transfer time, that is data transfer time..

and you do Y/X bcoz X > Y in your case..

now check both are given same result :)

The same thing written in 2 different conventions ..but at the end of the day both are correct.

0
yes this is exactly what I was saying, I was doing Total Cycle Time(40ns)/Data Transfer time(10ns), which if you take according to your convention would give same result, but here numerator is coming more than denominator even after taking everything logically correct, this is the thing I am asking?

Yes it was just the difference between what we were taking Preparation Time as..
5
i think memory cycle time is not suitable to be called as Data Preparation time as it is the time in which the actual data transfer is happening, whereas it is the DMA which actually prepares the data in its buffer.
0
Can you  please explain the role of main memory in this DMA operation.What I know is that during DMA the system bus is relinquished by the Cpu and then the transfer of data takes place,but how it is done i.e how disk is accessed or how the main memory is accessed,I don't know about,so if you could kindly explain that process.
0
@ Bikram

Why are you taking as x/y (pt/tt)

I think it should be transfer time / preparation time

As IO is a slow device so preparation time will always be higher than transfer time as in this question.

Preparation time = 39.06* 4 = 156.24ns (depends on IO)

Transfer time = 40 nsec

%time cpu blocked = 40/156.24*100 = 25%(approx)
0
@Komal16
Read all the comment carefully Bikram sir might have used different conventions. So, check that first.
0

Should we not assume by default that 1round = 1KB* 512* 16  data is read ??
Since generally all HDD read one track at a time but all the platters/surfaces together. In that case answer should be different.

0
Why we are not considering the fact that whenever 1 byte word is ready, it is sent to memory? Disk buffer is of 1B. Thus, we cannot accumulate 4B data in disk buffer and send it in one go. Also, we cannot do things in parallel. That is once disk buffer gets 1B data, it is output on system bus, then next byte and so on for 4 bytes. So, we need to send 1B at a time, even though bus width is 4B. So full 4B bandwidth of bus is never utilised and hence we need 4 cycles of 40 ns each, instead of 1 cycle of 40 ns. All this time system bus need to be reserved / stolen by DMA from processor. If disk buffer D would have larger than system bus S, we would have sent S bytes as soon as received and then next S bytes and so on, till all D bytes are sent. So parallelization can be done when disk buffer is bigger than bus width, but not when bus width is bigger than disk buffer. Or is it like there is some intermediate buffer wherein we empty the disk buffer. And only after 4B are there in intermediate buffer, we send it over system bus.
0

@Raj Singh 1 It is given in the question that we accumulate 4B and then transfer it.

My doubt is why we take 40ns to transfer all the 4B to the main memory. I mean to ask what is Memory cycle time? - Is it time to transfer only single byte at a time or to transfer all the available buffer at one go?

What if the buffer size were (say) 1MB? Will it take still 40ns for us to transfer the buffer data into main memory?

1

It says:

The disk interface reads a 4 byte word from the memory in each DMA cycle.

This gives bus width = 4B.

Then it says

Memory cycle time is 40 nsec.

Now we know, in one memory cycle, one bus wide data can be transferred. So 40 ns to send 4 byte word.

1

Cycle Stealing mode:

In cycle stealing mode we always follow pipelining concept that when one byte is getting transferred then Device is parallel preparing the next byte. “The fraction of CPU time to the data transfer time” if asked then cycle stealing mode is used.

Where, X µsec =data transfer time or preparation time (words/block)

Y µsec =memory cycle time or cycle time or transfer time (words/block)

% CPU idle (Blocked) ={ Y/ X }* 100

% CPU busy = {X / Y } * 100 Or,

% CPU busy = (100-% CPU Busy)

Burst mode:

X µsec =data transfer time or preparation time (words/block)

Y µsec =memory cycle time or cycle time or transfer time (words/block)

% CPU idle (Blocked) = {Y/ X+Y }x 100

% CPU busy = {X/ X+Y} x 100

0
doesn't cycle stealing works for 1 Byte?

transfer time of 4 Byte should be 40*4=160ns?

DMA cycle is not same as memory cycle right?
0

why did we consider by default pipeline here while we have not considered it here in this gate question

https://gateoverflow.in/3694/gate2004-it-51

B. 25

Does 3000 rotations in 60 seconds

$\implies$ 1 rotation in 20 ms

In 1 rotation covers data in 1 track which is = 512 × 1 KB
20 ms $\longleftrightarrow$ 512 KB
1 sec $\longleftrightarrow$ 25600 KB
$\implies$ Transfer rate = 25600 KBps
Transfer Rate means we can perform read or write operations(one at a time) with this speed.
In one DMA cycle of 40 ns we are able to transfer 4 Bytes to disk.

CPU Idle Time = 40 ns
Data Prepration Time = $\frac{4 Bytes}{25600 KB}$ = 156.25 ns

% Time CPU Blocked = $\frac{40 ns}{40 ns + 156.25 ns} \times 100$ = 20.382

0
how cpu idle time = 40ns?
0
because it's a cycle stealing mode.
1
thank God , I got the same answer as this..
0
Hi, Just one clarification.. In cycle stealing mode in each cycle 1 byte is transferred.. Then 1byte takes 40 nsec... Pls correct if my assumption is wrong..
0
In question it's mentioned writing in memory word size is 1 byte and reading is 4 byte word. Why have u taken word size as 4 bytes not as 1 byte?
1
Hi Rahulkr... it's 4byte for both reading and writing as per the question...
0
Hi  suman, I read this question from one gate book there it was given 1 byte, my mistake, thanks for replying and pointing out my mistake.
0
"whenever one 4 byte word is ready it is sent to memory" does it mean that DMA will hold the bus for 40ns, send the 4 byte and then release the bus?
Or
It sends 1 byte for every 10ns as=> 40ns/4bytes = 10ns?
And which one is the correct answer there are many answers below thank you.
5
Since we have 16 surfaces so do we not consider each surface while calculating data rate as each surface can have a head ?

So should the speed not be (16*25600) KBps ?
0
how total time is 40 ns + 156.25 ns??

please explain..why r we taking data preparation time here??

can someone tell me what is happening in 40 ns cycle tiime and what is happening in 156.25 ns??
4
DMA can transfer the data simultaneously while the disk operations are being done, total time will not include 40ns extra, % CPU blocked time=(40/156.25)x100 = 25.6%
0
if 156.25 ns is taken for data transfer then what happens in 40ns ?
3
cpu is not idle during DMA, it can do other tasks which doesnt need memory, So how is CPU blocked time 40ns??
0
rpm 3000 means

60/3000 = 1/50 sec roatate 1 track

track capacity = 512 * 1 KB

1/50 sec access 512 KB

1 byte access take 1/(50 * 512 * 2^10)  sec

4 byte access take 4/(512 * 2^10 ) sec

in stealing mode 4 byte take 40 n sec

so % cpu gets blocked = ( cycle stealing mode / cpu mode )

=   (40 * 10 ^ -9 *512 * 2^10 /4 ) *100 == 26 %
0
In one rotation we can parallely access data from all $16$ surfaces. So data accessed should be $16*512*1KB$

correct me if iam wrong
0
I am also thinking the same
0
why haven't u multiplied by 16 bcoz in one rotation it can cover all 16 surfaces ??
0

@sushmita I think the cpu should be idle. It may not access the system bus also since the DMA will be using it, and if does not access the system bus, then how can it carry out even the smaller RTL activities?

Rotation Speed = 3000 rpm = 50rps, 1round = $\frac{1}{50}$ seconds

Track Capacity = $512*1024 = 2^{19} =512KB$

Bytes to be transferred = 4B
Transfer Time =  $\frac{4}{50*512*1000}$ = 156.25ns  =4 memory cycles

So, One out of every 4 cycles will be stolen = that is 25% (CPU % Block)

It means CPU will only be blocked for 1 cycle, and for remaining 3 cycles it will be busy doing its own work!

edited

ans  is B.

Time takes for 1 rotation = 60/3000 . It reads 512*1 KBytes in one rotation (size of one track).

Time taken to read 4 bytes = [ 4/512 KB] * (60/300)  = 153 ns 153 is approximately  (160ns) .

Percentage of time CPU gets blocked = 40*100/160 = 25

rpm 3000 means

60/3000 = 1/50 sec roatate 1 track

track capacity = 512 * 1 KB

1/50 sec access 512 KB

1 byte access take 1/(50 * 512 * 2^10)  sec

4 byte access take 4/(512 * 2^10 ) sec

in stealing mode 4 byte take 40 n sec

so % cpu gets blocked = ( cycle stealing mode / cpu mode )

=   (40 * 10 ^ -9 *512 * 2^10 /4 ) *100 == 26 %
Time takes for 1 rotation = 60/3000
It reads 512*1024 Bytes in one rotation.
Time taken to read 4 bytes = 153 ns
153 is approximately 4 cycles (160ns)
Percentage of time CPU gets blocked = 40*100/160 = 25
0
Hi,

can you pls tell me what is happening in 40ns memory cycle and 153 ns time?i mean CPU will be idle for 40ns cycle time but what will it be doing during 153 ns??how is the total time 153??

can you pls clarify my doubts??
0
time taken to transfer 4 bytes is 4/(512*50*2^10)=152.58 ns almost 153 ns.Please clear concept on how tracks and sectors works you will understand.
0
actually i am confused that in cycle stealing mode,once the 1 byte is tranferred by DMA,it gives the control to CPU.so CPU is ideal for one cycle time but time taken to transfer  4 bytes is 153 by calculation ,so what will the CPU be doing in that time??
0
what work will be done in 40 ns by DMA if it takes 153 to transfer 4 bytes?? are you understanding my doubt??
1 vote

https://gateoverflow.in/1393/gate2005-70

B. 25

Does 3000 rotations in 60 seconds

⟹⟹ 1 rotation in 20 ms

In 1 rotation covers data in 1 track which is = 512 × 1 KB
20 ms ⟷⟷ 512 KB
1 sec ⟷⟷ 25600 KB
⟹⟹ Transfer rate = 25600 KBps
Transfer Rate means we can perform read or write operations(one at a time) with this speed.
In one DMA cycle of 40 ns we are able to transfer 4 Bytes to disk.

CPU Idle Time = 40 ns
Data Prepration Time = 4Bytes25600KB4Bytes25600KB = 156.25 ns

% Time CPU Blocked = 40ns40ns+156.25ns×10040ns40ns+156.25ns×100 = 20.382

1 vote
1 rotation take 60/3000 sec = 1/50 sec.

so (512*1KB) transfer in 1/50 sec. so transfer rate = (512*1KB*50) = 25600 KBSec.

Now we let 4x Bytes are transfer in whole process.

So Total Transfer time = 4x/(25600*10^3)sec = 156.25x nsec.

Now to calculate total cpu involvement time we need to consider total x time cpu involvement because there are total 4x byte we consider and each transferable data unit is 4 bytes.

So total CPU involvement time = x*40 nsec = 40x nsec.

% of cpu involvement  = {40x/(156.25*x)}*100 = 25.6%.

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