GATE CSE 2013 | Question: 28

Question

Consider the following sequence of micro-operations.

MBR ← PC  
MAR ← X  PC ← Y  
Memory ← MBR

Which one of the following is a possible operation performed by this sequence?

• A. Instruction fetch
• B. Operand fetch
• C. Conditional branch
• D. Initiation of interrupt service

Comments

https://cnx.org/contents/[email protected]:mur-kqun@1/Module-6-Control-Unit-Operation
Good read

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Good read : https://www.scesasaram.in/wp-content/uploads/2020/04/CSE_4_COA_2_Control-Unit.pdf

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Initiation of interrupt service

Answer 1

Here PC value is being stored in memory which is done when either CALL RETURN involved or there is Interrupt. As, we will have to come back to execute current instruction.

So, options (A), (B) are clearly incorrect.

Option (C) is incorrect because conditional branch does not require to save PC contents.

Option (D) is correct as it matches the generic Interrupt Cycle : 

 

$$\text{Interrupt Cycle:}$$

$$\begin{array}{lcl}
t_1:&\text{MBR}&\leftarrow(\text{PC})\\
t_2:&\text{MAR}&\leftarrow(\text{save-address})\\
&\text{PC}&\leftarrow(\text{routine-address})\\
t_3:&\text{Memory}&\leftarrow(\text{MBR})\\
\end{array}$$

Comments

@Pranavpurkar
what is MBR??

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@JAINchiNMay

it is Memory buffer register or memory data register , in which the data is stored before sending or receiving to/from memory.

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Thanks buddy!!

Answer 2

- whenever the word fetch is used instruction register was associated as there is no instruction reg. so (A) is not our answer.

- operand fetch says you have to get operand from the memory and place it into the memory data register so source should be the memory and destination should be memory data register so there no such operation is given so (B) is not our ans.

- in conditional branch or Unconditional branch you are able to place new value into the program counter but here it is doing one extra thing it is placing the old value of program counter into the memory so (C) is not our ans.

so our ans is (D)

Answer 3

PC holds the value of the next instruction to be executed we store the value of PC to the MBR and then to the memory .We are saving the value of PC in memory and new address value(routine address) is loaded in to the PC as interrupt is there as we have already save the PC in to the memory then why we are adding another address in to the PC. This can be done only in the Interrupt Services.

option (d) is correct

Answer 4

The interrupt cycle starts when there arises an interrupt signal. The PC has the address of the next instruction of the program that has to be executed next. The content of PC i.e. address of the next instruction that has to be executed is transferred to MBR. Now the content of MBR is written to a special memory location the address of which is loaded into MAR. Now the PC is initialized with the first instruction of interrupt service routine, this program’s services the occurred interrupts.

Answer 5

The Interrupt Cycle

At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred. If so, the interrupt cycle occurs. The nature of this cycle varies greatly from one machine to another. We present a very simple sequence of events, we have

t1 : MBR <= (PC)

t2 : MAR <= Save_Address

PC <= Routine_Address

t3: Memory <= (MBR)

In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for return from the interrupt. Then the MAR is loaded with the address at which the contents of the PC are to be saved, and the PC is loaded with the address of the start of the interrupt-processing routine. These two actions may each be a single micro-operation. However, because most processors provide multiple types and/or levels of interrupts, it may lake one or more additional micro-operations to obtain the save_address and the routine_address before they can be transferred to the MAR and PC, respectively. In any case, once this is done, the final step is to store the MBR, which contains the old value of the PC, into memory. The processor is now ready to begin the next instruction cycle.

source → https://cnx.org/contents/[email protected]:mur-kqun@1/Module-6-Control-Unit-Operation