We know :
a) Instruction execution time in a pipelined system = (k + n - 1) * tp + Branch penalty [ In case there is branch instructions
b) Normally if we go with RISC pipeline , branch target address is known at MA stage which is the 4th stage..Hence branch penalty per branch instruction = 3 cycles = 3 * tp
As here the instruction flow is I1 - I2 - I3 - I4 - I18 - I19 - I20 [ As it is given I4 is a branch instruction and branch address is corresponding to instruction I18 ]
So number of instructions involved in the sequence = 7
Number of stages in pipeline = 5
Thus total time taken = (k + n - 1) * tp + 3 * tp
= (5 + 7 - 1) * 2 + 3 * 2
= 22 + 6
= 28 ns
Hence required time = 28 ns
Suggested reading : https://gateoverflow.in/330/gate2013_45
P.S.: Unless and unless mentioned there will be uasge of some enhancement like hardware prefetching etc . , we have to assume that stalls are necessary as we need to know the address of the instruction where we are going to branch which is possible in MA stage only as far as RISC pipeline is concerned..As the naming of stages is not done in the question and it is a 5 stage pipeline we assume it is a RISC pipeline which is a standard and commonly used pipeline..
