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A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline is 5,and pipeline efficiency is 70% what is the speed up factor?

 

Please explain the Soultion and concept briefly i am little bit confused.
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 time taken by pipelined processor = n sec for 1 clock cycle (ideally we are considering that instruction are executed in 1 clock cycle)  and 5 instruction are executed in one cpi (mentioned at last line of question)

means time taken to execute 5 instruction in pipelined processor is sec

  and for sequential processor = 5 x 5 x n ( 5 x n  represent time per instruction in non pipelined processor multiplied by 5 instruction)

speed up = 25 n / n => 25

since efficiency is 70% speed up factor become 25 x (70/100) => 17.5

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