time taken by pipelined processor = n sec for 1 clock cycle (ideally we are considering that instruction are executed in 1 clock cycle) and 5 instruction are executed in one cpi (mentioned at last line of question)
means time taken to execute 5 instruction in pipelined processor is n sec
and for sequential processor = 5 x 5 x n ( 5 x n represent time per instruction in non pipelined processor multiplied by 5 instruction)
speed up = 25 n / n => 25
since efficiency is 70% speed up factor become 25 x (70/100) => 17.5