The un-pipelined processor has cycle time $25$ ns.
We evenly divided it into $5$ pipeline stage.
Pipeline latches has latency=$1$ ns
So cycle time in $5$-stage pipeline =$\large \frac{25}{5}+$ latches latency time =$\large 5+1=6 ns$ .
So total latency in pipeline=cycle time in pipeline * no of stage =$\large 5*6=30 ns$.
The un-pipelined processor has cycle time $25$ ns.
We evenly divided it into $50$ pipeline stage.
Pipeline latches has latency=$1$ ns
So cycle time in $50$-stage pipeline =$\large \frac{25}{50}+$ latches latency time =$\large 0.5+1=1.5 ns$ .
So total latency in pipeline=cycle time in pipeline * no of stage =$\large 1.5*50=75 ns$.