Pipeline Architecture

Question

if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the pipeline? how about if the processor is divided into 50 pipeline stages?

Answer 1

The un-pipelined processor has cycle time $25$ ns.

We evenly divided it into $5$ pipeline stage.

Pipeline latches has latency=$1$ ns

So cycle time in $5$-stage pipeline =$\large \frac{25}{5}+$ latches latency time =$\large 5+1=6 ns$ .

So total latency in pipeline=cycle time in pipeline * no of stage =$\large 5*6=30 ns$.

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The un-pipelined processor has cycle time $25$ ns.

We evenly divided it into $50$ pipeline stage.

Pipeline latches has latency=$1$ ns

So cycle time in $50$-stage pipeline =$\large \frac{25}{50}+$ latches latency time =$\large 0.5+1=1.5 ns$ .

So total latency in pipeline=cycle time in pipeline * no of stage =$\large 1.5*50=75 ns$.

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Comments

hi kabir, i thing this is correct answer..Thank you