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Consider this question and its selected answer:

And this question:

Both questions are somewhat similar.

In the first one's answer, instruction $I_1$ (when i = 2), the $S_2$ stage is started in 9th cycle and not 8th, because the result of previous instruction ($I_4$) is still in the $S_2$/$S_3$ buffer during 8th clock cycle.

While, in the answer of the second question, the $S_1$ stage of instruction $I_4$ (during first iteration), should start from clock 7, but the answer shows it in clock 6. Similarly with other instructions.

I am not getting why this difference? Is there any point that I am missing? 

PS. From where can I study this? Hamacher book doesn't contain pipelining in this much detail.

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After checking question

as @nitish said if multi buffer pipelined is allowed then only concept wise

this one is true, otherwise u need to wait for stall too.

Means if there is a stall means the previous stage is continuing

So, u cannot start next stage  in next instruction

Though in GATE question this doesnot follow, as per my knowledge

So, just follow

this answer.

I think GATE question follow multibuffer system , So, we havenot wait to still stall complete for an instruction, to start next stage.

Upto this I can tell,

I think ur doubt cleared

If more information I get , I will share

U can also share knowledge in this , if u get some information :)

Thanks. :)

@Rishabh Gupta 2 why in the 2009 question of your doubt asked we are not considering without loop level parallelism like why answer is not 30 ?


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