1 1 vote How to approach hit latency problems in cache mapping techniques. Please explain with an example. Thank in advance. CO & Architecture co-and-architecture cache-memory hit-latency + – AnilGoudar 1.2k views answer comment Share Follow Print See 1 comment 1 1 comment reply Surajit commented Nov 11, 2017 reply Follow flag can you post a question or make up a problem?is it regarding problems related to accessing multiple levels of cache and memory? 0 0 replyShare Please log in or register to add a comment.