The Gateway to Computer Science Excellence
0 votes
309 views
For a N-stage ripple carry counter which uses flipflops of propagation delay = P ns and clock period of C ns. Give the expression of the frequency of input signal?
in Digital Logic by Boss (10.7k points) | 309 views
0

in ripple counter, to work properly, Tclock is in prior adjusted as below given eqn

Tclock >= N*Tflip_flop

therefore entire input frequency will be frequency of input clock

therefore input frequency = $\frac{1}{C}$Ghz

0
So the following is incorrect. right?

$X = T_{clock} + N*T_{flipflop}$

$Input freq \leq  \frac{1}{X}   GHz$

In one of the madeeasy solutions this was given so I wanted to confirm.
+1
yes, it is incorrect.
0

Check this diagram.

0

So according to your diagram for this eqn. to satisfy

Tclock >= N*Tflip_flop

N must be 1.

Am I understanding it correctly? I'm weak in these timing diagrams.

Thanks

1 Answer

0 votes

Propagation delay for a Ripple counter is given by formula = 

Tpropagation−delay=n∗Tflipflops+Tcombinational.
Where Tpropagation−delay= 1/frequency(f)

where Strobe Signal's delay has to be treated as an additional Combinational crkt delay... 

by Active (1.5k points)
Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,737 questions
57,385 answers
198,542 comments
105,343 users