Number representation in 2's complement representation:
- Positive numbers as it is
- Negative numbers in $2's$ complement form.
So, the overflow conditions are
- When we add two positive numbers (sign bit $0$) and we get a sign bit $1$
- When we add two negative numbers (sign bit $1$) and we get sign bit $0$
- Overflow is relevant only for signed numbers and we use to carry for Unsigned numbers
- When the carryout bit and the carryin to the most significant bit differs
PS: When we add one positive and one negative number we won't get a carry. Also points $1$ and $2$ is leading to point $4$.
Now the question is a bit tricky. It is actually asking the condition of overflow of signed numbers when we use an adder which is meant to work for unsigned numbers.
So, if we see the options, B is the correct one here as the first part takes care of case 2 (negative numbers) and the second part takes care of case 1 (positive numbers) - point 4. We can see a counterexample each for other options:
A - Let $n=4$ and we do $0111 + 0111 = 1110$. This overflows as in $2's$ complement representation we can store only up to $7$. But the overflow condition in A returns false as $c_{out} = 0$.
$C$ - This works for the above example. But fails for $1001 + 0001 = 1010$ where there is no actual overflow $(-7+1 = -6)$, but the given condition gives an overflow as $c_{out} =0$ and $c_{n-1} = 1$.
D - This works for both the above examples, but fails for $1111 + 1111 = 1110$ $(-1 + -1 = -2)$ where there is no actual overflow but the given condition says so.
Reference: http://www.mhhe.com/engcs/electrical/hamacher/5e/graphics/ch02_025-102.pdf
Thanks, @Dilpreet for the link and correction.