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Misses in cache

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Consider a cache as follows:

  • Direct mapped
  • 8 words total cache data size
  • 2 words block size

A sequence of memory read is performed in the order shown from the following  addresses: 
0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 , 4 , 11.

Find No of compulsory misses and conflict misses and capacity misses.

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