Recent questions tagged misses / GATE Overflow for GATE CSE

1 votes

0 answers

1

Ace Test Series: CO & Architecture - Cache Misses Type

Na462

929 views

Na462 asked Jan 21, 2019

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0 answers

2

find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.

here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these loca...

bts1jimin

456 views

bts1jimin asked Jan 17, 2019

0 votes

1 answer

3

UPPCL AE 2018:21
Assume a memory access to main memory on a cache “miss” takes $30 \; \text{ns}$ and a memory access to the cache (on a cache “hit”) takes $3 \; \text{ns}.$ If $80 \%$ of the processor’s memory requests result in a cache “hit”, what is the average memory access time? $8.4 \text{ns}$ $9 \text{ns}$ $4.4 \text{ns}$ $2.2 \text{ns}$

Assume a memory access to main memory on a cache “miss” takes $30 \; \text{ns}$ and a memory access to the cache (on a cache “hit”) takes $3 \; \text{ns}.$ If $80...

admin

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admin asked Jan 5, 2019

0 votes

0 answers

4

ME TEST
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially ... i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?

Consider Prof. Vamshi‘s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 b...

newdreamz a1-z0

472 views

newdreamz a1-z0 asked Dec 25, 2018

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0 answers

5

Self doubt
Main mem block number is 4,6 and 8 . Then 8 is compalsory miss or conflict miss ????

Main mem block number is 4,6 and 8 . Then 8 is compalsory miss or conflict miss ????

abhishekmehta4u

233 views

abhishekmehta4u asked Sep 16, 2018

3 votes

2 answers

6

#Cache
Consider a direct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times. Q1) number of compulsory miss? Q2) number of conflict misses? Q3) The number of capacity misses?

Consider a direct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times.Q1) number o...

Ayan21

1.0k views

Ayan21 asked Sep 11, 2018

0 votes

0 answers

7

Misses
Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of hit rate and 200 cycles when hit in main memory to access a block. If main memory speed is improved 15%, then the improvement in L1 miss time is ________. (upto 2 decimal place)

Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2...

Na462

536 views

Na462 asked Jul 29, 2018

0 votes

1 answer

8

No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288

Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block ...

Na462

893 views

Na462 asked Jul 29, 2018

0 votes

0 answers

9

Number of Misses
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents number of compulsory and conflict misses? Ans. Compulsory = 3 and conflict = 18

Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks:Ox80000, Ox8000...

Na462

1.4k views

Na462 asked Jul 23, 2018

2 votes

1 answer

10

conflict miss
Can someone tell me the text-book definition for conflict miss?

Can someone tell me the text-book definition for conflict miss?

Warlock lord

1.7k views

Warlock lord asked Jan 12, 2018

0 votes

0 answers

11

Misses in cache
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 , 4 , 11. Find No of compulsory misses and conflict misses and capacity misses.

Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of memory read is performed in the order shown from the following addr...

Anjan

909 views

Anjan asked Dec 24, 2017

1 votes

1 answer

12

types of miss in cache
a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity misses?

a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity mis...

Raj_Choudhary

1.7k views

Raj_Choudhary asked Dec 4, 2017

1 votes

1 answer

13

Number of cache misses

pranab ray

836 views

pranab ray asked Nov 19, 2017

4 votes

1 answer

14

Conflict misses doubt.
I read that if block size increases, then we have fewer blocks so number of conflict misses increases. My doubt is how will the conflict misses increase ? If cache size is constant, then by increasing block size we have fewer blocks but SAME TAG ... blocks that would be mapped to each line of cache would be same and hence number of conflict misses should remain same right?

I read that if block size increases, then we have fewer blocks so number of conflict misses increases.My doubt is how will the conflict misses increase ? If cache size is...

Xylene

1.3k views

Xylene asked Aug 6, 2017

3 votes

1 answer

15

miss penalty
Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?

Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with ...

Akriti sood

1.9k views

Akriti sood asked Oct 31, 2016

19 votes

3 answers

16

difference between compulsory miss, conflict miss and capacity miss
I want to clearly understand the difference between compulsory miss, conflict miss and capacity miss what I understood is compulsory miss: when a block of main memory is trying to occupy fresh empty line of cache, it ... Because in associative mapping, no block of main memory tries to occupy already filled line. is this correct?

I want to clearly understand the difference between compulsory miss, conflict miss and capacity misswhat I understood iscompulsory miss: when a block of main memory is tr...

Anusha Motamarri

18.7k views

Anusha Motamarri asked Sep 22, 2016

1 votes

1 answer

17

Conflict Misses
Will conflict misses increase if k-way set associative cache is used and we increase the cache capacity?

Will conflict misses increase if k-way set associative cache is used and we increase the cache capacity?

Sumit1311

609 views

Sumit1311 asked Jan 21, 2016

0 votes

1 answer

18

MadeEasy Test Series: CO & Architecture - Conflict Misses
I have got - 5 compulsory misses for first 5 ref. - 3 conflict misses for last 3 ref.

I have got - 5 compulsory misses for first 5 ref.- 3 conflict misses for last 3 ref.

Tushar Shinde

1.1k views

Tushar Shinde asked Jan 18, 2016

12 votes

3 answers

19

direct mapping and types of misses
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of eight memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 Calculate No. of misses No of compulsory misses No. of conflict misses No. of capacity misses

Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of eight memory read is performed in the order shown from the following...

khushtak

6.4k views

khushtak asked Dec 15, 2015

9 votes

3 answers

20

page replacement
An 8 byte, 2-way set associative (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary): 0110, 0000, 0010, 0001, 0011, 0100, 1001, 0000, 1010, 1111, 0111 . How page replacement is done?What are the types of misses occured in this case?

An 8 byte, 2-way set associative (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary): 0110, 0000, 0010, 0001,...

Sara

3.4k views

Sara asked Oct 18, 2015

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