# Recent questions tagged misses

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here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.
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Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially cache is ... [i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?
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Consider a deirct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times. Q1) number of compulsory miss? Q2) number of conflict misses? Q3) The number of capacity misses?
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Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of hit rate and 200 cycles when hit in main memory to access a block. If main memory speed is improved 15%, then the improvement in L1 miss time is ________. (upto 2 decimal place)
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Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288
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Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents number of compulsory and conflict misses? Ans. Compulsory = 3 and conflict = 18
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Can someone tell me the text-book definition for conflict miss?
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Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 , 4 , 11. Find No of compulsory misses and conflict misses and capacity misses.
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a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity misses?
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I read that if block size increases, then we have fewer blocks so number of conflict misses increases. My doubt is how will the conflict misses increase ? If cache size is constant, then by increasing block size we have fewer blocks but SAME TAG bits . So the number of blocks that would be mapped to each line of cache would be same and hence number of conflict misses should remain same right?
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Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?
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I want to clearly understand the difference between compulsory miss, conflict miss and capacity miss what I understood is compulsory miss: when a block of main memory is trying to occupy fresh empty line of cache, it is called compulsory miss conflict miss: when ... set-associative cache. Because in associative mapping, no block of main memory tries to occupy already filled line. is this correct?
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