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Made Easy CA pipeline q2

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A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the throughout of the system if 20% of instructions are branch instructions ignore the overhead of buffer register. Each stage is having same amount of delay. The pipeline clock is 10ns Branch penality if of 4 cycles.

A.55 MIPS

B.45 MIPS

C. 65 MIPS

D. None of these.

(explain the solution as well)
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I tried the following way ...

For each of 20% of the NON OVERLAPPED instructions we are getting 4 stall cycles and therefore CPI for these instruction is 5

For other 80% of the OVERLAPPED instructions we are not getting any stalls and pipeline will output one instruction per cycle. There for in this case CPI = 1

Average CPI = $0.2*5 \ + \ 0.8*1 = 1.8$

So Throughput in MIPS = $\frac{1}{1.8*10*10^{-9}} \ * \frac{1}{10^{6}} = 55.55$

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Execution Time in Pipeline = (1+Number of Stall Per Instruction)*Cycle Time
=(1+4*0.2)10*10-9sec
=1.8*10-8 sec
Now, Throughput is number of instruction it can execute in 1 sec.
For 1 instruction if it take 1.8*10-8sec
then in 1 sec = 1/(1.8*10-8) = 55.55 MIPS

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