The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has 5 stages: IF, ID, EX, MA and WB and their is no data and control hazard. The number of clock cycles required for execution of sequence of instructions are
What i was thinking : (100+5-1)*1 + (25+5-1)*5+ (75+5-1)*3
Am i doing wrong?
Solution with explanation of formulae being used will be welcomed.