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consider two level cache hierarchies with L1 and L2 cache.Programs refer memory 1000 times out of which 40 misses are in L1 cache and 10 misses are in L2 cache.If the miss penalty of L2 is 200 clock cycles,hit time of L1 is 1 clock cycle,and hit time of L2 is 15 clock cycles,the average memory access time is__________clock cycles.

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miss penalty of L2

right?

plz check question
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Yes it is L2....updated that.
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+1

i am getting 3.6

@srestha shouldn't the hit rate of l2 be 30/40 and question clearly says heirarchical . so we must add miss penalty to second and third term.

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it should be
L1 access time+L1 miss %*L2 access time+L1 miss %*L2 miss %*memory time
here is is assumed miss penalty of L2=time required to bring the data from MM to L2 to L1 (as it is hierarchical)

=1 clock cycle+0.04*15+0.04*0.25*200
=3.6 clock cycles
PS-miss % of L2 will be 1/4. as L2 will be referred when there is miss in L1 cache. So hit % in L2=30/40

if it were simultaneous access then hit ratio of L2 would have been 990/1000

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@sandygate im getting the same too

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ok, thanks

but 10 misses in L2 out of 1000

right?

then how u got 0.25?

+1
in hierarchical arrangement, first L1 will be referred and when a block is not found in L1 then L2 will be referred right?
in L1 #hits=960 and number of misses=40. so for these 40 misses CPU will refer L2

now in L2 #misses=10
L2 will be accessed 40 times(because it is hierarchical)
so hit ratio of L2=30/40

and miss ratio in L2=10/40=0.25
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ok, thanks :)