Cache Memory

Question

consider two-level cache hierarchies with L1 and L2 cache. Programs refer to memory 1000 times out of which 40 misses are in the L1 cache and 10 misses are in the L2 cache.If the miss penalty of L2 is 200 clock cycles,hit time of L1 is 1 clock cycle,and hit time of L2 is 15 clock cycles,the average memory access time is__________clock cycles.

Comments

@aditi19

ok, thanks

but 10 misses in L2 out of 1000

right?

then how u got 0.25?

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in hierarchical arrangement, first L1 will be referred and when a block is not found in L1 then L2 will be referred right?
in L1 #hits=960 and number of misses=40. so for these 40 misses CPU will refer L2

now in L2 #misses=10
L2 will be accessed 40 times(because it is hierarchical)
so hit ratio of L2=30/40

and miss ratio in L2=10/40=0.25

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ok, thanks :)

Answer 1

T avg=1+ 40/100 * (15+ 10/40 *200) = 3.6 clock cycle.