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consider two-level cache hierarchies with L1 and L2 cache. Programs refer to memory 1000 times out of which 40 misses are in the L1 cache and 10 misses are in the L2 cache.If the miss penalty of L2 is 200 clock cycles,hit time of L1 is 1 clock cycle,and hit time of L2 is 15 clock cycles,the average memory access time is__________clock cycles.
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