1,120 views
0 votes
0 votes
A computer system has a page size of 1024 bytes and maintains page table for each process in the main memory.The overhead required for doing a lookup in the page table is $500ns$.To reduce this overhead, the computer has a TLB that caches 32 virtual pages to physical page frame mappings.A TLB lookup requires $100ns$.What TLB hit-rate is required to ensure an average virtual address translation time of $200ns$?

3 Answers

5 votes
5 votes
So, Average virtual address translation time(and not Average Memory Access time) is asked.

If TLB hit, it takes only 100ns

otherwise, it takes 100+500=600ns

$200=h(100)+(1-h)(600)$

$h=0.8$
1 votes
1 votes
It should be 0.8

Note that here, we are asked to calculate average virtual address translation time. So the equation would be like this:

Let the hit rate be $x$.

$200 = x(100) + (1-x)(100+500)$.

Solving this should get you the value of $x$ as $0.8$.

Here, we don't add the time to access the page from the memory because we only care about the address translation time.
0 votes
0 votes
OR we can do like this

P>>Hit rate

Avg access Time= Access time for TLB+(1-P)*(500)

200=100+(1-P)*500

100=500-500*P

500*P=400

P=0.8

Related questions

2 votes
2 votes
0 answers
3
2 votes
2 votes
1 answer
4
3lurryface asked Jan 9, 2019
1,049 views
If there is 2 or more level paging for processes, is it possible to have more than 1 page fault while accessing any single addressable unit(byte or word) ?