Memory Heirarchy Doubt

Question

Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) access time of 50ns and an access time of 5ns for each word thereafter. If the hit ratio of the cache memory is 95%, then average memory access time is_______.

 

 

When to consider a Strict memory hierarchy method or Parallel accessing method in Solving these types of questions? By Default which way is followed?

Comments

check my answer

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with the first formula getting incorrect answer.

I think the correct answer is 8.75 here (by applying hierarchical  access method ) but the thing how should we decide when to use hierarchical and when to use parallel access criteria?

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it will be given in the question, in case nothing is given then by default, we should consider Heirarchical access method

Answer 1

Given line size is 64 bytes there are 64/4=16 words [since word size is 4] in a cache line fetch and first word is of 4 bytes having access time 50 ns and remaining fifteen have access time 75 ns(i.e., 50+75=125 ns )

Tavg=timecache+(1−hitcache)[timememory]

=2.5+(1−.95)[125]

=2.5+6.25

=8.75

Comments

@Ashwani Yadav

One thing for sure.. either way you can interpret the question. Here the given statement favors more to hierarchical. But if you think it differently simultaneous also might work. GATE would mention it hopefully.

But if nothing is given, we should go with hierarchical method :)

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@Shamim Ahmed

why have u not multiplied 2.5 with 0.95 ?

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It would fetch same result only:

0.95*2.5+(1−.95)[2.5+125] = 8.75

Answer 2

level -> simultaneous access or parallel access-> H1(T1) +M1{(H2*T2) +(M2 * Tmemory)}

hierarchal  -> H1(T1) +M1[{H2*(T2+T1)} +{M2 * (T2+T1+Tmemory)}]

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In question

Consider a single level cache

it means first formula will apply but

Main Memory uses a block transfer capability that has a first word access time of 50ns and an access time of 5ns thereafter

this line means that first we search in cache

if hit then we access in 2.5ns

and

if a miss occurs then

-> we access 16 words and transfer it to cache and access it

-> first transfer takes 50ns and remaining 15 words take 5 ns each

-> So Tmemory = 50+(15*5) ns=50+75 ns = 125 ns.

-> and then we access the word from cache in 2.5ns

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hence H1 = 0.95

           T1= 2.5

           M1 = 1-0.95 =0.05

            Tmemory = 125ns.

H1(T1) +M1(Tmemory + T1)

=> 0.95*(2.5)+0.05*(125 + 2.5)

=>2.375 + 6.375

=> 8.75 ns

Comments

so what should we assume if nothing is given? Hierarchical access or parallel?

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hierarchial....

Don't mug up any formula except the one given below for these kind of questions.read each line of question then u will understand what to do. try to visualize what is happening,

Hit rate * ( how much time if hit occurs) + miss rate * (how much time if miss occurs)

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In question

Consider a single level cache

it means first formula will apply but

Any reference or reason as to why this is correct?