in CO and Architecture
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Consider a CPU contains 2000 instructions, there are 80 misses in L1  cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction is ________.

 

Can you please suggest the method to attempt such questions.

in CO and Architecture
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5.2 ?
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Its 9.36
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1 Answer

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Mem stall cycles due to misses per instruction

=(Miss rate in L1) ∗(Miss penalty of L1)

= (Miss rate in L1) ∗(Total time of L2)

= (Miss rate in L1) ∗(Hit Time of L2 + Miss Time of L2)

= (Miss rate in L1) ∗(Hit Time of L2 + ( Miss Rate of L2 * Miss penalty of L2 ))

= (80/2000) * ( 30 + ( 40/80 * 200 ))

=  (0.04) * ( 30 + ( 100 ))

=  (0.04) * ( 130)

5.2 Clock cycles

edited by

4 Comments

even i think answer should be 5.2..
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@BASANT KUMAR 

@Somoshree Datta 5

thanks for correcting me. i did not read the question properly. now corrected. please check.

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