ME OTS : Pipelining

Question

Consider the following statements

(I) Execution time for single instruction on six stage
pipelined CPU is less than or equal to identical non-
pipelined CPU.

(ii) In a uniform delay pipeline execution time for a
single instruction is equal to the execution time in
non-pipelined processor.

Which of the above statements are correct ?

 

Answer : 2nd statement is correct.

 

Doubt :

Nothing is mentioned about stage delay and if stage delay exist then for single execution, pipeline time will not be equal. Hence 2nd statement wont be true always.

Comments

@HeadShot

https://www.geeksforgeeks.org/computer-organization-and-architecture-pipelining-set-3-types-and-stalling/

it is mentioned separately , 

If buffers are included between the stages then, Cycle Time (Tp) = Stage Delay + Buffer Delay

but i think if not mentioned , we don't need to consider

 

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@prashant jha 1

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https://www.geeksforgeeks.org/gate-gate-cs-2000-question-8/

this might help . :)