1,282 views
2 2 votes

cache memory question

Given ans is :248

Acc to me ans sholud be like this:

cache can hold 64 blocks without replacement .

cpu fetches words from 0-4351 so no of blocks required is: 4352/64= 68 blocks

1st time 68 miss operation occured. but after this step i got stuck.

please explain how to solve such type of ques.

1 Answer

Best answer
7 7 votes
first of all make a clear picture of problem. like

cache size = 4K word

cache block = 4K word / 64 word =64 blocks

no of sets = 64 / 4 = 16 sets each having 64 cache blocks and each cache block can contain 64 words

now same for the main memory.

main memory size = 32K word

main memory blocks = 32K word/ 64 word = 512 blocks each having 64 words

in 68 main memory blocks we can put all 4352 word

now you can apply set associative mapping eaisly

ans is :- 248

set0     0    16    32    48      
set1     1    17    33    49      
set2     2    18    34    50
set3     3    19    35    51
set4     4    20    36    52
            :      :       :       :
            :      :       :       :
            :      :       :       :
           14    30    46    62
set15  15    31    47    63

it is using LRU so in set 0 block 0 replace by 64

set 1 block 1 replace by 65

set 2 block 2 replace by 66

set 3 block 3 replace by 67

hence 68 misses

now it will repeat again then 20 misses will occur each time

all the blocks are in cache except block 0, 1, 2, 3

in set 0 block 16 replace by 0

set 1 block 17 replace by 1

set 2 block  18 replace by 2

set 3 block 19 replace by 3

4 missing

and now block 16 17 18 19 are missing

so

in set 0 block 31 replace by 16

set 1 block 32 replace by 17

set 2 block  33 replace by 18

set 3 block 34 replace by 19

4 missing

and now block 31 32 33 34 are missing

so

in set 0 block 48 replace by 31

set 1 block 49 replace by 32

set 2 block  50replace by 33

set 3 block 51 replace by 34

4 missing

and now block 48 49 50 51 are missing

so

in set 0 block 64 replace by 48

set 1 block 65 replace by 49

set 2 block  66 replace by 50

set 3 block 67 replace by 51

4 missing

and now block 64 65 66 67 are missing

so

in set 0 block 0 replace by 64

set 1 block 1 replace by 65

set 2 block  2 replace by 66

set 3 block 3 replace by 67

4 missing

total = 4 + 4+ 4 + 4+ 4 =20 misses in second iteration

now it will repeat again then 20 misses will occur each time

so 20*9 = 180

total = 180+68 = 248
• selected by
Position:
Show:

Related questions

0 0 votes
1 1 answer
63
63 views
DΛΞMON asked 2 days ago
63 views
$\begin{array}{l}\textbf{Q. } \text{A processor has the cache hierarchy as given. Assume that 20\% of instructions are}\\\text{load/store instructions. The remaining 80\%...
2 2 votes
1 1 answer
151
151 views
naveendewangan asked Aug 2
151 views
Assume 15% of L1 misses are resolved in the victim cache. If retrieving data from the victim cache takes 4 cycles and retrieving data from main memory take 50 cycles, by ...
1 1 vote
1 1 answer
232
232 views
Ultra_Instinct_AM asked Jan 7
232 views
A processor has a base CPI of 1.2. Every instruction requires one instruction fetch, and 30% of instructions are loads and 10% are stores.The L1 cache miss rate (same for...