All the CLR inputs are connected to active-low connection,i.e when it gets voltage "0" as input,it get's activated and resets all the Flip-Flops.
Now,as the last one is a NAND gate,it will output zero if both of the inputs are fed as "1".Now,the first time the output of Qc & Qd becomes 1, the NAND gate outputs 0 and the CLR input is activated,and the Flip-Flops get resetted. Equivalently,it's a MOD-12 asynchronous-up-counter as it as 12 distinct counting states from(0000 - 1011).As soon as the output becomes 1100 the upper 2 bits(Qd &Qc becomes 11 & the FF's are resetted).
