The Gateway to Computer Science Excellence
First time here? Checkout the FAQ!
x
+1 vote
52 views
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
in Digital Logic by Boss (10.2k points) | 52 views
0

ripple carry between the modules

means?? 

Please log in or register to answer this question.

Related questions

0 votes
1 answer
1
asked Dec 31, 2018 in CO and Architecture by amitqy Active (1.8k points) | 102 views
+1 vote
0 answers
2
asked May 9 in Operating System by Hirak Active (3.4k points) | 83 views
Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
49,823 questions
54,821 answers
189,571 comments
81,053 users