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Digital logic- nptel assignment

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Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.

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Answer is 24.

Basic gate delay δ = 2 nsec

Delay of the 2-level 64-bit carry lookahead adder will be

TCLA = (6 + 2 ceiling{log4 64} ) δ = 12 δ = 12 x 2nsec = 24 nsec
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