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add \$so,\$to,\$t1

sub \$t2,\$S0,\$t3  

Num of stall cyles i am getting 2 stall but the books says 3

1.No data data forwarding

2.Write to register file in first half and read from second half in clock cycle  my timing dig goes like this

add  IF ID EX MEM WB     

             NOP        

                   NOP           

                            IF ID  EXE .....
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This will be the timing diagram. Three stall cycles are needed to ensure WB is completed before the ID stage of the SUB instruction. This assumes Register File read is performed during the ID stage of the pipeline.

  Clk1 Clk2 Clk3 Clk4 Clk5 Clk6 Clk7 Clk8 Clk9
ADD IF ID EX MEM WB        
SUB   IF Stall Stall Stall ID EX MEM WB


        

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