Pipeline Stalls

Question

What is the idea behind introducing pipeline stalls ?

On getting some instructions and stages How can one construct pipeline cycle

Eg:

I1 : LOAD R0,loc
I2  : ADD r0,r0

I3 : Add r2 , r0

Stages

Instruction Fectch
Instruction Decode
Execute
Memory Access
Write Back

Answer 1

That's the simplest way to take care of dependency. For pipeline to run without any problem for any instruction, it should not have any dependency with 'k' neighboring instructions where 'k' is the number of pipeline stages. If there is a dependency from ith stage to jth stage (i < j), j-i-1 delay slots (pipeline stalls during these) are introduced so that ith stage eventually gets the required data from jth one.

 

For the given code, I2 depends on I1 for R0. More specifically ID stage (during which register is read) of I1 depends on WB stage of I0. So, (5 - 2 -1) = 2 delay slots are needed.

I3 also depends on I2. More specifically ID stage depends on WB stage (when registers are updated) of I2. So, again 2 delay slots are needed.

If we can do operand forwarding- where the required data is directly passed from a stage to a stage of new instruction, we can avoid stalls in many cases. For this example, we can pass data from Memory Access Stage to EX stage for I1-I2 (this still requires 1 delay) and from the output of EX stage of I2 to EX stage of I3 (no more stalls required).