I am very Confused to how to calculate Delay SLOTS in a given Pipeline.
Can anybody explain the technique for finding the number of delay slots and Stalls in A pipelined processor.
2. Is delay slot and pipeline stall the same thing. Because delay slot is created using branch instruction and stall means just that pipeline stage is empty at that moment due to dependency but logically both are the same thing right??? .
Like in https://gateoverflow.in/1818/gate2006-42
How do we get 2 delay slot according to me it should be 3.
For Example :-
Say the five stages are = F,D,E,M,W and 2nd instruction is the branch instruction and branch target is the Instruction 4 then:-
I1 = F D E M W
I2 = F D E M W
I3 = F D --- --- ---
I4 = F D E M W
So 3 stalls right? what about Pipeline stalls??
Plz explain where i am wrong?
