ISRO CSE 2020 | Question: 11

Question

Minimum number of NAND gates required to implement the following binary equation

$Y = (\overline{A}+\overline{B})(C+D)$

• A. $4$
• B. $5$
• C. $3$
• D. $6$

Comments

option A is correct

Answer 1

Answer is (a) 4

Comments

How even this circuit come in mind?

Give a logic!!!

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Y=(A’+B’)(C+D)

TRY TO WRITE IN  De Morgan's LAW

A’+B’ = (AB)’   USING THIS WE CAN WRITE AND THIS REPRESENT 1 NAND GATE

Y=(AB)’(C+D)

Y=(AB)’C+(AB)’D

AGAIN WRITE IN  De Morgan's LAW

(AB)’C+(AB)’D = (((AB)’C)’.((AB)’D)’)’       

hence 1 nand gate for (AB)’ 

1 for ((AB)’.C)’

1 for ((AB)’.D)’

and 1 for (((AB)’C)’.((AB)’D)’)’     

TOTAL 4 NAND gates. 

 

 

 

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Great 😊😊

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best aproach..

Answer 2

AND-OR (or SOP)realization is easily convertible into NAND-NAND realization.
NOT-OR is equivalent to NAND.
Y = (A’+B’) (C+D)
Y = (A’+B’)C + (A’+B’)D
Let X= (A’+B’) , Y= C, and Z= D
One NAND gate is needed for implementing X= (A’ + B’).
Y= XY + XZ
Y= [(XY)’ (XZ)’]’
Three NAND gates are needed for [(XY)’ (XZ)’]’.
Total Four NAND gates are required to implement thY = (A’+B’) (C+D).

Comments

@topper98
Very nice explanation.

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Nice Explanation

 

Answer 3

clearly observe the question it is x-or representation using POS , so minimum NAND gates required to implement xor gate is  4.