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Consider the following data path diagram.

Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ indicate read and write operations, respectively.

1. $R2_{r},\text{ TEMP1}_{r},ALU_{\text{add}}, \text{ TEMP2}_{w}$
2. $R1_{r},\text{ TEMP1}_{w}$
3. $PC_{r}, \text{ MAR}_{w}, \text{ MEM}_{r}$
4. $\text{ TEMP2}_{r}, \text{ R0}_{w}$
5. $\text{ MDR}_{r}, \text{ IR}_{w}$

Which one of the following is the correct order of execution of the above steps?

1. $2,1,4,5,3$
2. $1,2,4,3,5$
3. $3,5,2,1,4$
4. $3,5,1,2,4$

$3^{rd}$ followed by $5^{th}$ are Instruction fetch cycle micro operations and can be elaborated as follows:

$t_{1}:\text{MAR}_{w}\leftarrow \text{PC}_{r}$

$t_{2}:\text{MDR}_{w}\leftarrow \text{Memory}_{r}\mid \text{PC}\leftarrow \text{PC}+1$

$t_{3}:\text{IR}_{w}\leftarrow \text{MDR}_{r}$

Now we need to perform Execute cycle micro operations. Just observe the figure and it will be very easy to identify the sequence between $1^{st},2^{nd},4^{th}$

$2^{nd}$ is clearly stating that we need to move $\text{R1}$ content to some temporary register named as $\text{TEMP1}$ and it is very clear that before performing $\text{ALU}$ operation we need the content in $\text{TEMP1}.$ Hence $2^{nd}$ will be performed next after $5^{th}.$

$\text{TEMP1}_{w}\leftarrow \text{R1}_{r}$

Now we can perform ALU operation and can take second operand directly from $R2$ and the figure clearly shows us that we need to put the result of ALU back into $\text{TEMP2}.$ All these steps are performed in $1^{st}.$ So $1^{st}$ will be next.

$\text{TEMP2}_{w}\leftarrow \text{TEMP1}_{r}\ +_{\text{ALU}_{add}}\ \text{R2}_{r}$

Lastly we need to put the result present in $\text{TEMP2}$ into $\text{R0}.$ This step is performed by $4^{th}.$

$\text{R0}_{w}\leftarrow \text{TEMP2}_{r}$

Correct Answer $(C): 3,5,2,1,4$

### 1 comment

one input line of the ALU is missing in the structure?

Here, First Instruction We will put the instruction address into the MAR register so we can fetch instruction from the memory.

This can be done by, PCr, MARw,MEMr

After Fetching the instruction from the memory, Instruction place in to the MBR register and from MBR to IR register it moves for execution.

This can be done by, MDRr, IRw

When instruction reaches to IR register, Decoder will start decoding of the instruction and it will find that first R1 register has to be fetched and put into the first temporary register.

This can be done by, R1r,Temp1w

After that, we have to fetch operand from the second register. After fetching both the operand ALU will start its work and stores result in the temporary register.

This can be done by, R2r,Temp1r,ALUadd,Temp2w

And at the last result stores into the destination register.

This can be done by, Temp2r,R0w.

So sequence is : 3,5,2,1,4

can sequence 2,1,4,3,5 be also correct ?

@sanjaysharmarose no bro , because without instruction fetch and decode how would you know which operation to perform !!

option c is the right answer

3-store content of pc into memory address register and issue memory read

5-store the data from memory data register into instruction register.

2-store the content of R1 into temporary register TEMP1

1-add contents of R2 and TEMP1  and store result in TEMP2.

4- store contents of TEMP2 into R0

To perform addition of R1 and R2 and store it in R0,

We have to consider following points.

1. We have to read the Program Counter to see which is the next instruction to be executed. This will always be our first step. Simultaneously, during the same instruction, we will write the address fetched from PC into MAR and then increment our program counter by 4Bytes(1 word). This can also be depicted as

MAR ← PC

PC ←PC+1

2. After going to the location(address) specified in the MAR, we will read the data stored at that particular address and we will write this data into Memory data register.

MDR ← MAR[data]

In the same instruction cycle, We will write the Instruction register for the next instruction to be executed.

3.This value from the MDR will be passed on to the Temp1 register for temporary addition purposes in later stages.

4. Now we will read R2 and read the contents of TEMP1 register, add them and store it in  TEMP2 register

TEMP2 ← TEMP1[data] + R2[data]

5. Finally we will read the value from Temp2 register and write it to R0 register.

R0 ← TEMP2

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