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rsansiya111 asked in CO and Architecture Dec 19, 2021

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rsansiya111 asked in Mathematical Logic Dec 18, 2021

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Geeks Quiz
S1 : Loss of ACK from client doesn’t effect on termination of connection. S2 : The client moves FIN-Wait-1 → FIN-Wait-2 → closed in the state machine on no packet loss. S3 : Loss of ACK from server restrict termination of connection. Options Are: S1 and S2 S2 and S3 S1 and S3 S2 only

rsansiya111 asked in Computer Networks Dec 18, 2021

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rsansiya111 asked in Theory of Computation Dec 18, 2021

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Geeks quiz
Options are: 100 200 50 400

rsansiya111 asked in Spatial Aptitude Dec 18, 2021

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GATE CSE 1988 | Question: 9ii
The code for the implementation of a sub-routine to convert positive numeric data from binary to appropriate character string in a $PDP-11$ like machine has been given below Note-that $SP$ is the stack pointer and $R_i$ represents $i^{th}$ ...

go_editor asked in CO and Architecture Dec 19, 2016

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GATE CSE 1988 | Question: 5i
A ROM has the following time parameters: Maximum Address to valid Data Output delay $= 30$ n sec. Maximum Chip Select to valid Data Output delay $= 20$ n sec. Maximum Data Hold time (after address change or after chip deselect) $= 10$ n ... negligible What is the maximum rate at which a CPU can continuously read data from this ROM? (Show your calculations step-by-step)

go_editor asked in CO and Architecture Dec 19, 2016

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GATE CSE 1988 | Question: 4i
An $8$-bit data path is to be set up using two $4$-bit ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two ... a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.

go_editor asked in CO and Architecture Dec 19, 2016

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GATE CSE 1988 | Question: 2xi
A modern day machine typically has an atomic TEST AND SET instruction. Why?

go_editor asked in Operating System Dec 18, 2016

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GATE CSE 1989 | Question: 10b
Consider the following grammar for variable declarations: <vardecl> $\rightarrow$ <vardecl><idlist> : <type>; <vardecl> $\rightarrow \in$ <idlist> $\rightarrow$ <idlist>, id <idlist> ... necessary. Make suitable assumptions regarding procedures operating on the symbol table; you need not elaborate upon these procedures.

makhdoom ghaya asked in Compiler Design Dec 5, 2016

by makhdoom ghaya

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1 vote

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GATE CSE 1989 | Question: 6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU ... would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.

makhdoom ghaya asked in CO and Architecture Dec 1, 2016

by makhdoom ghaya

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GATE CSE 1989 | Question: 5b
It is required to implement a stack using bidirectional shift registers providing stack underflow and overflow detection capability. How many shift registers are needed for a stack capacity of $nk$-bit words? Show the schematic diagram of the implementation, clearly indicating all the data and control lines.

makhdoom ghaya asked in Digital Logic Dec 1, 2016

by makhdoom ghaya

448 views

3 votes

1 answer

13

GATE CSE 1989 | Question: 4-xi
Express the following list in terms of a linked list structure suitable for internal representation. $(((ab)c)d((e)))$

makhdoom ghaya asked in DS Nov 30, 2016

by makhdoom ghaya

596 views

1 vote

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GATE CSE 1989 | Question: 4-vi
Consider the definition of macro $B,$ nested within the definition of a macro $A.$ Can a call to macro $B$ also appear within macro $A?$ If not, why not? If yes, explain if there are any restrictions.

makhdoom ghaya asked in Compiler Design Nov 30, 2016

by makhdoom ghaya

587 views

1 vote

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GATE CSE 1990 | Question: 16b
Consider the grammar: $G_{2}$: Para $\rightarrow$ Sentence RP | Sentence RP $\rightarrow$ b Sentence RP | b Sentence Sentence $\rightarrow$ Word b Sentence | Word Word $\rightarrow$ letter * word | letter letter $\rightarrow$ ... to use a stack algorithm to parse the following string$id*id\;b\; id * id$ The parse should generate a rightmost derivation.

makhdoom ghaya asked in Compiler Design Nov 26, 2016

by makhdoom ghaya

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1 vote

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GATE CSE 1990 | Question: 14
The following algorithm (written in pseudo-pascal) work on an undirected graph $G$ program Explore (G) procedure Visit (u) begin if Adj (u) is not empty {comment:Adj (u) is the list of edges incident to u} then begin Select an edge from ... that each vertex can be accessed and removed from LIST in constant time. Also, show that all edges of the graph are traversed.

makhdoom ghaya asked in Algorithms Nov 26, 2016

by makhdoom ghaya

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1 vote

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GATE CSE 1990 | Question: 12a
Consider the following instance of the $0 -1$ Knapsack problem: $\max\; 6X_{1} + 11X_{2} + 16X_{3} + 21X_{4} + 26X_{5}$ Subject to $4X_{1} + 8X_{2} + 12X_{3} + 16X_{4} + 20 X_{5} < 32$ and $X_{i}=0$ ... nodes in the tree in the order in which they are expanded and for each node show the bound on the partial solutions and the decision which leads to that node.

makhdoom ghaya asked in Algorithms Nov 25, 2016

by makhdoom ghaya

730 views

2 votes

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GATE CSE 1990 | Question: 9a
Assume that an instruction test-and-set (TS) has been provided in a machine whose function is as follows: 'the left most bit of the one byte operand is checked and accordingly the condition code (CC) is set to $1$ or $0$. After checking and setting the condition code, implement a critical region using this instruction.

makhdoom ghaya asked in Operating System Nov 24, 2016

by makhdoom ghaya

657 views

1 vote

0 answers

19

GATE CSE 1987 | Question: 3a
Design an $8 \times 8$ multiplier using five $4$-bits adders and $4$ ROM's each programmed to realise $4 \times 4$ multiplier.

makhdoom ghaya asked in Digital Logic Nov 12, 2016

by makhdoom ghaya

488 views

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20

GATE CSE 1991 | Question: 07b
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume ... bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.

go_editor asked in CO and Architecture Apr 24, 2016

652 views

1 vote

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GATE CSE 1992 | Question: 05,b
Three devices $A, B$ and $C$ are connected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INTR$1,$ INTR$2$ and INTR$3$ are available with priority of INTR$1 >$ priority ... priority logic, using an interrupt mask register, in which Priority of $A$ > Priority of $B$ > Priority of $C.$

Arjun asked in CO and Architecture Dec 19, 2015

by Arjun

620 views

5 votes

0 answers

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GATE CSE 1994 | Question: 23
Suppose we have a computer with single register and only three instructions given below: ... $T \rightarrow (E)\mid id$ Write a syntax directed translation to generate code using this grammar for the computer described above.

Kathleen asked in Compiler Design Oct 6, 2014

846 views

4 votes

0 answers

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GATE CSE 1997 | Question: 23
The language $L,$ defined by the following grammar, allows use of real or integer data in expressions and assignment statements. <assign-stmt> :: <LHS> := <E> <E> ::= <E> + <T>|<T> <T> :: ... that the name and type of variable can be obtained by making the function calls' give_name $(id)$ and give_type $(id)$ respectively.

Kathleen asked in Compiler Design Sep 29, 2014

1.1k views

2 votes

0 answers

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GATE CSE 1991 | Question: 07a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.

Kathleen asked in CO and Architecture Sep 13, 2014

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