GATE CSE 2020 | Question: 3

Question

Consider the following statements.

1. Daisy chaining is used to assign priorities in attending interrupts.
2. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
3. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
4. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

• A. Ⅰ and Ⅱ only
• B. Ⅰ and Ⅳ only
• C. Ⅰ and Ⅲ only
• D. Ⅲ only

Comments

opt d is wrong as 

In Direct Memory Access (DMA), either the CPU or the DMA controller can control the bus at any given time, but not both simultaneously. The bus control is transferred to the DMA controller when it initiates a data transfer.

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@arjun sir ,For statement 2,  if multiple vectored interrupt requests are raised in a system where no daisy chaining method is there and also only 1 INTR and 1 INCA pin is present then doesn't Cpu use polling method to find who raised the interrupt request otherwise how cpu will know the source ? Then statement 2 would have been correct, right?

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Can anyone please answer the above @scar_witch_25 question?

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@Kush_Bhatt You are asking about non vectored interrupts ( which uses polling ) . But in vectored interrupt polling is not required , it directly sends address through address bus . In a vectored interrupt, even if there is only one INTR line , The device that wins priority (via hardware arbitration) will supply the vector.

 

Answer 1

Answer : C

I is true

• The daisy-chaining method of establishing priority consists of a serial connection of all devices that request an interrupt. The device with the highest priority is placed in the first position, followed by lower-priority devices up to the device with the lowest priority, which is placed last in the chain.

II. is false

• Vectored interrupts are achieved by assigning each interrupting device a unique code, typically four to eight bits in length. When a device interrupts, it sends its unique code over the data bus to the processor, telling the processor which interrupt service routine to execute.

III. is true 

• The process of periodically checking status bits to see if it is time for the next I/O operation, is called polling. Polling is the simplest way for an I/O device to communicate with the processor the processor. 

IV. is false 

• Since CPU release bus only after getting request from DMA and get after DMA release the BUS.

Comments

@Prashant. This question comes under which subject? CAO or OS?I have done OS but I am not able to solve this question from what i studied in OS.Does this question require COA knowledge?

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It comes under COA . The topics are "Types of Interrupt" and "Data transfer in DMA".

Check out the below links:

https://nptel.ac.in/content/storage2/courses/108105057/Pdf/Lesson-15.pdf

https://nptel.ac.in/content/storage2/courses/108105057/Pdf/Lesson-16.pdf

https://www.elprocus.com/direct-memory-access-dma-in-computer-architecture/#:~:text=The%20term%20DMA%20stands%20for,minimal%20intervention%20from%20the%20processor.

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Good reference to understand Daisy chaining:

https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/

Answer 2

Polling vs interrupt

Interrupts are asynchronous and triggered by external devices. The CPU does not need to actively check the status bits in this case.

 

Instead, the device signals the CPU via an interrupt line (e.g., INTR) when it needs attention.

The CPU acknowledges the interrupt after completing the current instruction and services the interrupt using an Interrupt Service Routine (ISR).

Polling:

In polling, the CPU actively checks the status bits of I/O devices to determine if they need attention.

Example: The CPU might repeatedly read a device's status register to see if a flag (like "data ready") is set.

So,polling is done from cpu side to check whether an io device needs attention.

Interrupt is generated by an io device to indicate the CPU's attention required.

Options

1.True. Daisy chaining is a method of assigning priorities to devices in a chain. The device closer to the CPU in the chain has higher priority, as it gets the interrupt acknowledgment signal first.

2.false. a vectored interrupt, the interrupting device provides a unique vector (address of the interrupt service routine) directly to the CPU. Polling is not required.Polling is not required in the typical case of vectored interrupts, even with multiple interrupt sources. However, in certain scenarios where multiple vectored interrupts occur simultaneously, the need for polling might arise.(When it is difficult for CPU to identify which device interrupted it.)

3.True. Polling involves the CPU actively checking the status registers of devices to see if they need service.

4.False. During DMA (Direct Memory Access), the CPU relinquishes control of the bus to the DMA controller. Only one device can be the bus master at a time to prevent bus contention.