GATE IT 2007 | Question: 41

Question

Following table indicates the latencies of operations between the instruction producing the result and instruction using the result.
$$\begin{array}{|l|l|c|} \hline \textbf {Instruction producing the result} &  \textbf{Instruction using the result }& \textbf{Latency} \\\hline \text{ALU Operation} & \text{ALU Operation} & 2 \\\hline \text{ALU Operation} & \text{Store} & \text{2}\\\hline \text{Load} & \text{ALU Operation} & \text{1}\\\hline \text{Load} & \text{Store} & \text{0} \\\hline \end{array}$$

Consider the following code segment:

 Load R1, Loc 1; Load R1 from memory location Loc1
 Load R2, Loc 2; Load R2 from memory location Loc 2
 Add R1, R2, R1; Add R1 and R2 and save result in R1
 Dec R2;         Decrement R2
 Dec R1;         Decrement R1
 Mpy R1, R2, R3; Multiply R1 and R2 and save result in R3
 Store R3, Loc 3; Store R3 in memory location Loc 3

What is the number of cycles needed to execute the above code segment assuming each instruction takes one cycle to execute?

• A. $7$
• B. $10$
• C. $13$
• D. $14$

Comments

What is the answer ? 13 or 14?

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instruction i4 is decrementing i.e arithmatic operation it is betn LOAD and ALU operation so latency is 1

you havnt included that ...

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No.The explanation given above is correct and answer is 13 only.

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I3 is ALU operation which uses result of LOAD in I2 , so latency is of 1 cycle (after I2)

I4 is ALU operation which uses result of LOAD in I2 , so latency is of 1 cycle (after I2) but I3 is executing at cycle 4. Therefore. I4 will execute at cycle no. 5.

I5 is ALU operation using result of ALU in I3 therefore has to wait for 2 cycles after I3

I6 is ALU and uses result of ALU in I5 ,therefore waits 2 cycles

Answer 1

explanation using clock cycle graph