GATE IT 2006 | Question: 8

Question

Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

• A. Transparent DMA and Polling interrupts
• B. Cycle-stealing and Vectored interrupts
• C. Block transfer and Vectored interrupts
• D. Block transfer and Polling interrupts

Comments

Does High CPU bandwidth means that, CPU is least idle or CPU is very busy?
Also, does high I/O bandwidth mean that, I/O device can transfer very high amount of data in a fixed time?

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In Transparent DMA CPU is most busy. How does it relate to High CPU bandwidth? Please expalin

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In Transparent DMA CPU is most busy it means it can send more data in a fixed amount of time(Bandwidth is nothing but how much data is transferred in a fixed amount of data) therefore Bandwidth of CPU will be high in case of Transparent DMA

Answer 1

CPU  get highest bandwidth in transparent DMA and polling. but it asked for I/O bandwidth not cpu bandwidth so option (A) is wrong.

In case of Cycle stealing, in each cycle time device send data then wait again after few CPU cycle it sends to memory . So option (B) is wrong.

In case of Polling CPU takes the initiative so I/O bandwidth can not be high so option (D) is wrong .

Consider Block transfer, in each single block device send data so bandwidth ( means the amount of data ) must be high . This makes option (C) correct.

Answer 2

The answer is option C .

In block transfer the entire block of data is transfered then only CPU again becomes the bus master

And in vectored Interrupts . I/o device along with interrupts send vector address of Interrupt Service routine which guides CPU to execute for a specific I/O device

Hence in both case BW will be required in a good amount !

Comments

Consider Cycle stealing, in each cycle time device send data then wait again after few CPU cycle it sends to memory . So option B is wrong.

Also CPU will get highest bandwidth in transparent DMA and polling. but it asked for I/O bandwidth not cpu bandwidth so option A is wrong.

In case of Polling CPU takes the initiative so I/O bandwidth can not be high so option D is wrong .

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Thank you sir.!

Could you please explain transparent DMA and why is CPU BW high for that?

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Tuhin Dutta

Could you please explain transparent DMA and why is CPU BW high for that?

In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses.